Line data Source code
1 : /* SPDX-License-Identifier: GPL-2.0 */
2 : #ifndef _ASM_X86_MCE_H
3 : #define _ASM_X86_MCE_H
4 :
5 : #include <uapi/asm/mce.h>
6 :
7 : /*
8 : * Machine Check support for x86
9 : */
10 :
11 : /* MCG_CAP register defines */
12 : #define MCG_BANKCNT_MASK 0xff /* Number of Banks */
13 : #define MCG_CTL_P BIT_ULL(8) /* MCG_CTL register available */
14 : #define MCG_EXT_P BIT_ULL(9) /* Extended registers available */
15 : #define MCG_CMCI_P BIT_ULL(10) /* CMCI supported */
16 : #define MCG_EXT_CNT_MASK 0xff0000 /* Number of Extended registers */
17 : #define MCG_EXT_CNT_SHIFT 16
18 : #define MCG_EXT_CNT(c) (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
19 : #define MCG_SER_P BIT_ULL(24) /* MCA recovery/new status bits */
20 : #define MCG_ELOG_P BIT_ULL(26) /* Extended error log supported */
21 : #define MCG_LMCE_P BIT_ULL(27) /* Local machine check supported */
22 :
23 : /* MCG_STATUS register defines */
24 : #define MCG_STATUS_RIPV BIT_ULL(0) /* restart ip valid */
25 : #define MCG_STATUS_EIPV BIT_ULL(1) /* ip points to correct instruction */
26 : #define MCG_STATUS_MCIP BIT_ULL(2) /* machine check in progress */
27 : #define MCG_STATUS_LMCES BIT_ULL(3) /* LMCE signaled */
28 :
29 : /* MCG_EXT_CTL register defines */
30 : #define MCG_EXT_CTL_LMCE_EN BIT_ULL(0) /* Enable LMCE */
31 :
32 : /* MCi_STATUS register defines */
33 : #define MCI_STATUS_VAL BIT_ULL(63) /* valid error */
34 : #define MCI_STATUS_OVER BIT_ULL(62) /* previous errors lost */
35 : #define MCI_STATUS_UC BIT_ULL(61) /* uncorrected error */
36 : #define MCI_STATUS_EN BIT_ULL(60) /* error enabled */
37 : #define MCI_STATUS_MISCV BIT_ULL(59) /* misc error reg. valid */
38 : #define MCI_STATUS_ADDRV BIT_ULL(58) /* addr reg. valid */
39 : #define MCI_STATUS_PCC BIT_ULL(57) /* processor context corrupt */
40 : #define MCI_STATUS_S BIT_ULL(56) /* Signaled machine check */
41 : #define MCI_STATUS_AR BIT_ULL(55) /* Action required */
42 : #define MCI_STATUS_CEC_SHIFT 38 /* Corrected Error Count */
43 : #define MCI_STATUS_CEC_MASK GENMASK_ULL(52,38)
44 : #define MCI_STATUS_CEC(c) (((c) & MCI_STATUS_CEC_MASK) >> MCI_STATUS_CEC_SHIFT)
45 :
46 : /* AMD-specific bits */
47 : #define MCI_STATUS_TCC BIT_ULL(55) /* Task context corrupt */
48 : #define MCI_STATUS_SYNDV BIT_ULL(53) /* synd reg. valid */
49 : #define MCI_STATUS_DEFERRED BIT_ULL(44) /* uncorrected error, deferred exception */
50 : #define MCI_STATUS_POISON BIT_ULL(43) /* access poisonous data */
51 : #define MCI_STATUS_SCRUB BIT_ULL(40) /* Error detected during scrub operation */
52 :
53 : /*
54 : * McaX field if set indicates a given bank supports MCA extensions:
55 : * - Deferred error interrupt type is specifiable by bank.
56 : * - MCx_MISC0[BlkPtr] field indicates presence of extended MISC registers,
57 : * But should not be used to determine MSR numbers.
58 : * - TCC bit is present in MCx_STATUS.
59 : */
60 : #define MCI_CONFIG_MCAX 0x1
61 : #define MCI_IPID_MCATYPE 0xFFFF0000
62 : #define MCI_IPID_HWID 0xFFF
63 :
64 : /*
65 : * Note that the full MCACOD field of IA32_MCi_STATUS MSR is
66 : * bits 15:0. But bit 12 is the 'F' bit, defined for corrected
67 : * errors to indicate that errors are being filtered by hardware.
68 : * We should mask out bit 12 when looking for specific signatures
69 : * of uncorrected errors - so the F bit is deliberately skipped
70 : * in this #define.
71 : */
72 : #define MCACOD 0xefff /* MCA Error Code */
73 :
74 : /* Architecturally defined codes from SDM Vol. 3B Chapter 15 */
75 : #define MCACOD_SCRUB 0x00C0 /* 0xC0-0xCF Memory Scrubbing */
76 : #define MCACOD_SCRUBMSK 0xeff0 /* Skip bit 12 ('F' bit) */
77 : #define MCACOD_L3WB 0x017A /* L3 Explicit Writeback */
78 : #define MCACOD_DATA 0x0134 /* Data Load */
79 : #define MCACOD_INSTR 0x0150 /* Instruction Fetch */
80 :
81 : /* MCi_MISC register defines */
82 : #define MCI_MISC_ADDR_LSB(m) ((m) & 0x3f)
83 : #define MCI_MISC_ADDR_MODE(m) (((m) >> 6) & 7)
84 : #define MCI_MISC_ADDR_SEGOFF 0 /* segment offset */
85 : #define MCI_MISC_ADDR_LINEAR 1 /* linear address */
86 : #define MCI_MISC_ADDR_PHYS 2 /* physical address */
87 : #define MCI_MISC_ADDR_MEM 3 /* memory address */
88 : #define MCI_MISC_ADDR_GENERIC 7 /* generic */
89 :
90 : /* CTL2 register defines */
91 : #define MCI_CTL2_CMCI_EN BIT_ULL(30)
92 : #define MCI_CTL2_CMCI_THRESHOLD_MASK 0x7fffULL
93 :
94 : #define MCJ_CTX_MASK 3
95 : #define MCJ_CTX(flags) ((flags) & MCJ_CTX_MASK)
96 : #define MCJ_CTX_RANDOM 0 /* inject context: random */
97 : #define MCJ_CTX_PROCESS 0x1 /* inject context: process */
98 : #define MCJ_CTX_IRQ 0x2 /* inject context: IRQ */
99 : #define MCJ_NMI_BROADCAST 0x4 /* do NMI broadcasting */
100 : #define MCJ_EXCEPTION 0x8 /* raise as exception */
101 : #define MCJ_IRQ_BROADCAST 0x10 /* do IRQ broadcasting */
102 :
103 : #define MCE_OVERFLOW 0 /* bit 0 in flags means overflow */
104 :
105 : #define MCE_LOG_MIN_LEN 32U
106 : #define MCE_LOG_SIGNATURE "MACHINECHECK"
107 :
108 : /* AMD Scalable MCA */
109 : #define MSR_AMD64_SMCA_MC0_CTL 0xc0002000
110 : #define MSR_AMD64_SMCA_MC0_STATUS 0xc0002001
111 : #define MSR_AMD64_SMCA_MC0_ADDR 0xc0002002
112 : #define MSR_AMD64_SMCA_MC0_MISC0 0xc0002003
113 : #define MSR_AMD64_SMCA_MC0_CONFIG 0xc0002004
114 : #define MSR_AMD64_SMCA_MC0_IPID 0xc0002005
115 : #define MSR_AMD64_SMCA_MC0_SYND 0xc0002006
116 : #define MSR_AMD64_SMCA_MC0_DESTAT 0xc0002008
117 : #define MSR_AMD64_SMCA_MC0_DEADDR 0xc0002009
118 : #define MSR_AMD64_SMCA_MC0_MISC1 0xc000200a
119 : #define MSR_AMD64_SMCA_MCx_CTL(x) (MSR_AMD64_SMCA_MC0_CTL + 0x10*(x))
120 : #define MSR_AMD64_SMCA_MCx_STATUS(x) (MSR_AMD64_SMCA_MC0_STATUS + 0x10*(x))
121 : #define MSR_AMD64_SMCA_MCx_ADDR(x) (MSR_AMD64_SMCA_MC0_ADDR + 0x10*(x))
122 : #define MSR_AMD64_SMCA_MCx_MISC(x) (MSR_AMD64_SMCA_MC0_MISC0 + 0x10*(x))
123 : #define MSR_AMD64_SMCA_MCx_CONFIG(x) (MSR_AMD64_SMCA_MC0_CONFIG + 0x10*(x))
124 : #define MSR_AMD64_SMCA_MCx_IPID(x) (MSR_AMD64_SMCA_MC0_IPID + 0x10*(x))
125 : #define MSR_AMD64_SMCA_MCx_SYND(x) (MSR_AMD64_SMCA_MC0_SYND + 0x10*(x))
126 : #define MSR_AMD64_SMCA_MCx_DESTAT(x) (MSR_AMD64_SMCA_MC0_DESTAT + 0x10*(x))
127 : #define MSR_AMD64_SMCA_MCx_DEADDR(x) (MSR_AMD64_SMCA_MC0_DEADDR + 0x10*(x))
128 : #define MSR_AMD64_SMCA_MCx_MISCy(x, y) ((MSR_AMD64_SMCA_MC0_MISC1 + y) + (0x10*(x)))
129 :
130 : #define XEC(x, mask) (((x) >> 16) & mask)
131 :
132 : /* mce.kflags flag bits for logging etc. */
133 : #define MCE_HANDLED_CEC BIT_ULL(0)
134 : #define MCE_HANDLED_UC BIT_ULL(1)
135 : #define MCE_HANDLED_EXTLOG BIT_ULL(2)
136 : #define MCE_HANDLED_NFIT BIT_ULL(3)
137 : #define MCE_HANDLED_EDAC BIT_ULL(4)
138 : #define MCE_HANDLED_MCELOG BIT_ULL(5)
139 :
140 : /*
141 : * Indicates an MCE which has happened in kernel space but from
142 : * which the kernel can recover simply by executing fixup_exception()
143 : * so that an error is returned to the caller of the function that
144 : * hit the machine check.
145 : */
146 : #define MCE_IN_KERNEL_RECOV BIT_ULL(6)
147 :
148 : /*
149 : * Indicates an MCE that happened in kernel space while copying data
150 : * from user. In this case fixup_exception() gets the kernel to the
151 : * error exit for the copy function. Machine check handler can then
152 : * treat it like a fault taken in user mode.
153 : */
154 : #define MCE_IN_KERNEL_COPYIN BIT_ULL(7)
155 :
156 : /*
157 : * This structure contains all data related to the MCE log. Also
158 : * carries a signature to make it easier to find from external
159 : * debugging tools. Each entry is only valid when its finished flag
160 : * is set.
161 : */
162 : struct mce_log_buffer {
163 : char signature[12]; /* "MACHINECHECK" */
164 : unsigned len; /* = elements in .mce_entry[] */
165 : unsigned next;
166 : unsigned flags;
167 : unsigned recordlen; /* length of struct mce */
168 : struct mce entry[];
169 : };
170 :
171 : /* Highest last */
172 : enum mce_notifier_prios {
173 : MCE_PRIO_LOWEST,
174 : MCE_PRIO_MCELOG,
175 : MCE_PRIO_EDAC,
176 : MCE_PRIO_NFIT,
177 : MCE_PRIO_EXTLOG,
178 : MCE_PRIO_UC,
179 : MCE_PRIO_EARLY,
180 : MCE_PRIO_CEC,
181 : MCE_PRIO_HIGHEST = MCE_PRIO_CEC
182 : };
183 :
184 : struct notifier_block;
185 : extern void mce_register_decode_chain(struct notifier_block *nb);
186 : extern void mce_unregister_decode_chain(struct notifier_block *nb);
187 :
188 : #include <linux/percpu.h>
189 : #include <linux/atomic.h>
190 :
191 : extern int mce_p5_enabled;
192 :
193 : #ifdef CONFIG_ARCH_HAS_COPY_MC
194 : extern void enable_copy_mc_fragile(void);
195 : unsigned long __must_check copy_mc_fragile(void *dst, const void *src, unsigned cnt);
196 : #else
197 : static inline void enable_copy_mc_fragile(void)
198 : {
199 : }
200 : #endif
201 :
202 : struct cper_ia_proc_ctx;
203 :
204 : #ifdef CONFIG_X86_MCE
205 : int mcheck_init(void);
206 : void mcheck_cpu_init(struct cpuinfo_x86 *c);
207 : void mcheck_cpu_clear(struct cpuinfo_x86 *c);
208 : void mcheck_vendor_init_severity(void);
209 : int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info,
210 : u64 lapic_id);
211 : #else
212 1 : static inline int mcheck_init(void) { return 0; }
213 4 : static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {}
214 0 : static inline void mcheck_cpu_clear(struct cpuinfo_x86 *c) {}
215 : static inline void mcheck_vendor_init_severity(void) {}
216 : static inline int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info,
217 : u64 lapic_id) { return -EINVAL; }
218 : #endif
219 :
220 : #ifdef CONFIG_X86_ANCIENT_MCE
221 : void intel_p5_mcheck_init(struct cpuinfo_x86 *c);
222 : void winchip_mcheck_init(struct cpuinfo_x86 *c);
223 : static inline void enable_p5_mce(void) { mce_p5_enabled = 1; }
224 : #else
225 : static inline void intel_p5_mcheck_init(struct cpuinfo_x86 *c) {}
226 : static inline void winchip_mcheck_init(struct cpuinfo_x86 *c) {}
227 : static inline void enable_p5_mce(void) {}
228 : #endif
229 :
230 : void mce_setup(struct mce *m);
231 : void mce_log(struct mce *m);
232 : DECLARE_PER_CPU(struct device *, mce_device);
233 :
234 : /* Maximum number of MCA banks per CPU. */
235 : #define MAX_NR_BANKS 64
236 :
237 : #ifdef CONFIG_X86_MCE_INTEL
238 : void mce_intel_feature_init(struct cpuinfo_x86 *c);
239 : void mce_intel_feature_clear(struct cpuinfo_x86 *c);
240 : void cmci_clear(void);
241 : void cmci_reenable(void);
242 : void cmci_rediscover(void);
243 : void cmci_recheck(void);
244 : #else
245 : static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { }
246 : static inline void mce_intel_feature_clear(struct cpuinfo_x86 *c) { }
247 : static inline void cmci_clear(void) {}
248 : static inline void cmci_reenable(void) {}
249 : static inline void cmci_rediscover(void) {}
250 : static inline void cmci_recheck(void) {}
251 : #endif
252 :
253 : int mce_available(struct cpuinfo_x86 *c);
254 : bool mce_is_memory_error(struct mce *m);
255 : bool mce_is_correctable(struct mce *m);
256 : int mce_usable_address(struct mce *m);
257 :
258 : DECLARE_PER_CPU(unsigned, mce_exception_count);
259 : DECLARE_PER_CPU(unsigned, mce_poll_count);
260 :
261 : typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS);
262 : DECLARE_PER_CPU(mce_banks_t, mce_poll_banks);
263 :
264 : enum mcp_flags {
265 : MCP_TIMESTAMP = BIT(0), /* log time stamp */
266 : MCP_UC = BIT(1), /* log uncorrected errors */
267 : MCP_DONTLOG = BIT(2), /* only clear, don't log */
268 : };
269 : bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b);
270 :
271 : int mce_notify_irq(void);
272 :
273 : DECLARE_PER_CPU(struct mce, injectm);
274 :
275 : /* Disable CMCI/polling for MCA bank claimed by firmware */
276 : extern void mce_disable_bank(int bank);
277 :
278 : /*
279 : * Exception handler
280 : */
281 : void do_machine_check(struct pt_regs *pt_regs);
282 :
283 : /*
284 : * Threshold handler
285 : */
286 : extern void (*mce_threshold_vector)(void);
287 :
288 : /* Deferred error interrupt handler */
289 : extern void (*deferred_error_int_vector)(void);
290 :
291 : /*
292 : * Used by APEI to report memory error via /dev/mcelog
293 : */
294 :
295 : struct cper_sec_mem_err;
296 : extern void apei_mce_report_mem_error(int corrected,
297 : struct cper_sec_mem_err *mem_err);
298 :
299 : /*
300 : * Enumerate new IP types and HWID values in AMD processors which support
301 : * Scalable MCA.
302 : */
303 : #ifdef CONFIG_X86_MCE_AMD
304 :
305 : /* These may be used by multiple smca_hwid_mcatypes */
306 : enum smca_bank_types {
307 : SMCA_LS = 0, /* Load Store */
308 : SMCA_LS_V2, /* Load Store */
309 : SMCA_IF, /* Instruction Fetch */
310 : SMCA_L2_CACHE, /* L2 Cache */
311 : SMCA_DE, /* Decoder Unit */
312 : SMCA_RESERVED, /* Reserved */
313 : SMCA_EX, /* Execution Unit */
314 : SMCA_FP, /* Floating Point */
315 : SMCA_L3_CACHE, /* L3 Cache */
316 : SMCA_CS, /* Coherent Slave */
317 : SMCA_CS_V2, /* Coherent Slave */
318 : SMCA_PIE, /* Power, Interrupts, etc. */
319 : SMCA_UMC, /* Unified Memory Controller */
320 : SMCA_PB, /* Parameter Block */
321 : SMCA_PSP, /* Platform Security Processor */
322 : SMCA_PSP_V2, /* Platform Security Processor */
323 : SMCA_SMU, /* System Management Unit */
324 : SMCA_SMU_V2, /* System Management Unit */
325 : SMCA_MP5, /* Microprocessor 5 Unit */
326 : SMCA_NBIO, /* Northbridge IO Unit */
327 : SMCA_PCIE, /* PCI Express Unit */
328 : N_SMCA_BANK_TYPES
329 : };
330 :
331 : #define HWID_MCATYPE(hwid, mcatype) (((hwid) << 16) | (mcatype))
332 :
333 : struct smca_hwid {
334 : unsigned int bank_type; /* Use with smca_bank_types for easy indexing. */
335 : u32 hwid_mcatype; /* (hwid,mcatype) tuple */
336 : u8 count; /* Number of instances. */
337 : };
338 :
339 : struct smca_bank {
340 : struct smca_hwid *hwid;
341 : u32 id; /* Value of MCA_IPID[InstanceId]. */
342 : u8 sysfs_id; /* Value used for sysfs name. */
343 : };
344 :
345 : extern struct smca_bank smca_banks[MAX_NR_BANKS];
346 :
347 : extern const char *smca_get_long_name(enum smca_bank_types t);
348 : extern bool amd_mce_is_memory_error(struct mce *m);
349 :
350 : extern int mce_threshold_create_device(unsigned int cpu);
351 : extern int mce_threshold_remove_device(unsigned int cpu);
352 :
353 : void mce_amd_feature_init(struct cpuinfo_x86 *c);
354 : int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr);
355 :
356 : #else
357 :
358 : static inline int mce_threshold_create_device(unsigned int cpu) { return 0; };
359 : static inline int mce_threshold_remove_device(unsigned int cpu) { return 0; };
360 : static inline bool amd_mce_is_memory_error(struct mce *m) { return false; };
361 : static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { }
362 : static inline int
363 : umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) { return -EINVAL; };
364 : #endif
365 :
366 : static inline void mce_hygon_feature_init(struct cpuinfo_x86 *c) { return mce_amd_feature_init(c); }
367 : #endif /* _ASM_X86_MCE_H */
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