Line data    Source code

       1             : // SPDX-License-Identifier: GPL-2.0
       2             : #include <linux/linkage.h>
       3             : #include <linux/errno.h>
       4             : #include <linux/signal.h>
       5             : #include <linux/sched.h>
       6             : #include <linux/ioport.h>
       7             : #include <linux/interrupt.h>
       8             : #include <linux/irq.h>
       9             : #include <linux/timex.h>
      10             : #include <linux/random.h>
      11             : #include <linux/kprobes.h>
      12             : #include <linux/init.h>
      13             : #include <linux/kernel_stat.h>
      14             : #include <linux/device.h>
      15             : #include <linux/bitops.h>
      16             : #include <linux/acpi.h>
      17             : #include <linux/io.h>
      18             : #include <linux/delay.h>
      19             : #include <linux/pgtable.h>
      20             : 
      21             : #include <linux/atomic.h>
      22             : #include <asm/timer.h>
      23             : #include <asm/hw_irq.h>
      24             : #include <asm/desc.h>
      25             : #include <asm/io_apic.h>
      26             : #include <asm/acpi.h>
      27             : #include <asm/apic.h>
      28             : #include <asm/setup.h>
      29             : #include <asm/i8259.h>
      30             : #include <asm/traps.h>
      31             : #include <asm/prom.h>
      32             : 
      33             : /*
      34             :  * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts:
      35             :  * (these are usually mapped to vectors 0x30-0x3f)
      36             :  */
      37             : 
      38             : /*
      39             :  * The IO-APIC gives us many more interrupt sources. Most of these
      40             :  * are unused but an SMP system is supposed to have enough memory ...
      41             :  * sometimes (mostly wrt. hw bugs) we get corrupted vectors all
      42             :  * across the spectrum, so we really want to be prepared to get all
      43             :  * of these. Plus, more powerful systems might have more than 64
      44             :  * IO-APIC registers.
      45             :  *
      46             :  * (these are usually mapped into the 0x30-0xff vector range)
      47             :  */
      48             : 
      49             : DEFINE_PER_CPU(vector_irq_t, vector_irq) = {
      50             :         [0 ... NR_VECTORS - 1] = VECTOR_UNUSED,
      51             : };
      52             : 
      53           1 : void __init init_ISA_irqs(void)
      54             : {
      55           1 :         struct irq_chip *chip = legacy_pic->chip;
      56           1 :         int i;
      57             : 
      58             :         /*
      59             :          * Try to set up the through-local-APIC virtual wire mode earlier.
      60             :          *
      61             :          * On some 32-bit UP machines, whose APIC has been disabled by BIOS
      62             :          * and then got re-enabled by "lapic", it hangs at boot time without this.
      63             :          */
      64           1 :         init_bsp_APIC();
      65             : 
      66           1 :         legacy_pic->init(0);
      67             : 
      68          18 :         for (i = 0; i < nr_legacy_irqs(); i++)
      69          16 :                 irq_set_chip_and_handler(i, chip, handle_level_irq);
      70           1 : }
      71             : 
      72           1 : void __init init_IRQ(void)
      73             : {
      74           1 :         int i;
      75             : 
      76             :         /*
      77             :          * On cpu 0, Assign ISA_IRQ_VECTOR(irq) to IRQ 0..15.
      78             :          * If these IRQ's are handled by legacy interrupt-controllers like PIC,
      79             :          * then this configuration will likely be static after the boot. If
      80             :          * these IRQs are handled by more modern controllers like IO-APIC,
      81             :          * then this vector space can be freed and re-used dynamically as the
      82             :          * irq's migrate etc.
      83             :          */
      84          17 :         for (i = 0; i < nr_legacy_irqs(); i++)
      85          16 :                 per_cpu(vector_irq, 0)[ISA_IRQ_VECTOR(i)] = irq_to_desc(i);
      86             : 
      87           1 :         BUG_ON(irq_init_percpu_irqstack(smp_processor_id()));
      88             : 
      89           1 :         x86_init.irqs.intr_init();
      90           1 : }
      91             : 
      92           1 : void __init native_init_IRQ(void)
      93             : {
      94             :         /* Execute any quirks before the call gates are initialised: */
      95           1 :         x86_init.irqs.pre_vector_init();
      96             : 
      97           1 :         idt_setup_apic_and_irq_gates();
      98           1 :         lapic_assign_system_vectors();
      99             : 
     100           1 :         if (!acpi_ioapic && !of_ioapic && nr_legacy_irqs()) {
     101             :                 /* IRQ2 is cascade interrupt to second interrupt controller */
     102           1 :                 if (request_irq(2, no_action, IRQF_NO_THREAD, "cascade", NULL))
     103           0 :                         pr_err("%s: request_irq() failed\n", "cascade");
     104             :         }
     105           1 : }