Line data Source code
1 : // SPDX-License-Identifier: GPL-2.0
2 : /*
3 : * Intel Multiprocessor Specification 1.1 and 1.4
4 : * compliant MP-table parsing routines.
5 : *
6 : * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
7 : * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
8 : * (c) 2008 Alexey Starikovskiy <astarikovskiy@suse.de>
9 : */
10 :
11 : #include <linux/mm.h>
12 : #include <linux/init.h>
13 : #include <linux/delay.h>
14 : #include <linux/memblock.h>
15 : #include <linux/kernel_stat.h>
16 : #include <linux/mc146818rtc.h>
17 : #include <linux/bitops.h>
18 : #include <linux/acpi.h>
19 : #include <linux/smp.h>
20 : #include <linux/pci.h>
21 :
22 : #include <asm/io_apic.h>
23 : #include <asm/acpi.h>
24 : #include <asm/irqdomain.h>
25 : #include <asm/mtrr.h>
26 : #include <asm/mpspec.h>
27 : #include <asm/proto.h>
28 : #include <asm/bios_ebda.h>
29 : #include <asm/e820/api.h>
30 : #include <asm/setup.h>
31 : #include <asm/smp.h>
32 :
33 : #include <asm/apic.h>
34 : /*
35 : * Checksum an MP configuration block.
36 : */
37 :
38 2 : static int __init mpf_checksum(unsigned char *mp, int len)
39 : {
40 2 : int sum = 0;
41 :
42 294 : while (len--)
43 292 : sum += *mp++;
44 :
45 2 : return sum & 0xFF;
46 : }
47 :
48 4 : static void __init MP_processor_info(struct mpc_cpu *m)
49 : {
50 4 : int apicid;
51 4 : char *bootup_cpu = "";
52 :
53 4 : if (!(m->cpuflag & CPU_ENABLED)) {
54 0 : disabled_cpus++;
55 0 : return;
56 : }
57 :
58 4 : apicid = m->apicid;
59 :
60 4 : if (m->cpuflag & CPU_BOOTPROCESSOR) {
61 1 : bootup_cpu = " (Bootup-CPU)";
62 1 : boot_cpu_physical_apicid = m->apicid;
63 : }
64 :
65 4 : pr_info("Processor #%d%s\n", m->apicid, bootup_cpu);
66 4 : generic_processor_info(apicid, m->apicver);
67 : }
68 :
69 : #ifdef CONFIG_X86_IO_APIC
70 1 : static void __init mpc_oem_bus_info(struct mpc_bus *m, char *str)
71 : {
72 1 : memcpy(str, m->bustype, 6);
73 1 : str[6] = 0;
74 1 : apic_printk(APIC_VERBOSE, "Bus #%d is %s\n", m->busid, str);
75 1 : }
76 :
77 1 : static void __init MP_bus_info(struct mpc_bus *m)
78 : {
79 1 : char str[7];
80 :
81 1 : mpc_oem_bus_info(m, str);
82 :
83 : #if MAX_MP_BUSSES < 256
84 : if (m->busid >= MAX_MP_BUSSES) {
85 : pr_warn("MP table busid value (%d) for bustype %s is too large, max. supported is %d\n",
86 : m->busid, str, MAX_MP_BUSSES - 1);
87 : return;
88 : }
89 : #endif
90 :
91 1 : set_bit(m->busid, mp_bus_not_pci);
92 1 : if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA) - 1) == 0) {
93 : #ifdef CONFIG_EISA
94 : mp_bus_id_to_type[m->busid] = MP_BUS_ISA;
95 : #endif
96 0 : } else if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI) - 1) == 0) {
97 0 : clear_bit(m->busid, mp_bus_not_pci);
98 : #ifdef CONFIG_EISA
99 : mp_bus_id_to_type[m->busid] = MP_BUS_PCI;
100 : } else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA) - 1) == 0) {
101 : mp_bus_id_to_type[m->busid] = MP_BUS_EISA;
102 : #endif
103 : } else
104 0 : pr_warn("Unknown bustype %s - ignoring\n", str);
105 1 : }
106 :
107 1 : static void __init MP_ioapic_info(struct mpc_ioapic *m)
108 : {
109 1 : struct ioapic_domain_cfg cfg = {
110 : .type = IOAPIC_DOMAIN_LEGACY,
111 : .ops = &mp_ioapic_irqdomain_ops,
112 : };
113 :
114 1 : if (m->flags & MPC_APIC_USABLE)
115 1 : mp_register_ioapic(m->apicid, m->apicaddr, gsi_top, &cfg);
116 1 : }
117 :
118 0 : static void __init print_mp_irq_info(struct mpc_intsrc *mp_irq)
119 : {
120 0 : apic_printk(APIC_VERBOSE,
121 : "Int: type %d, pol %d, trig %d, bus %02x, IRQ %02x, APIC ID %x, APIC INT %02x\n",
122 : mp_irq->irqtype, mp_irq->irqflag & 3,
123 : (mp_irq->irqflag >> 2) & 3, mp_irq->srcbus,
124 : mp_irq->srcbusirq, mp_irq->dstapic, mp_irq->dstirq);
125 0 : }
126 :
127 : #else /* CONFIG_X86_IO_APIC */
128 : static inline void __init MP_bus_info(struct mpc_bus *m) {}
129 : static inline void __init MP_ioapic_info(struct mpc_ioapic *m) {}
130 : #endif /* CONFIG_X86_IO_APIC */
131 :
132 2 : static void __init MP_lintsrc_info(struct mpc_lintsrc *m)
133 : {
134 2 : apic_printk(APIC_VERBOSE,
135 : "Lint: type %d, pol %d, trig %d, bus %02x, IRQ %02x, APIC ID %x, APIC LINT %02x\n",
136 : m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbusid,
137 : m->srcbusirq, m->destapic, m->destapiclint);
138 2 : }
139 :
140 : /*
141 : * Read/parse the MPC
142 : */
143 1 : static int __init smp_check_mpc(struct mpc_table *mpc, char *oem, char *str)
144 : {
145 :
146 1 : if (memcmp(mpc->signature, MPC_SIGNATURE, 4)) {
147 0 : pr_err("MPTABLE: bad signature [%c%c%c%c]!\n",
148 : mpc->signature[0], mpc->signature[1],
149 : mpc->signature[2], mpc->signature[3]);
150 0 : return 0;
151 : }
152 1 : if (mpf_checksum((unsigned char *)mpc, mpc->length)) {
153 0 : pr_err("MPTABLE: checksum error!\n");
154 0 : return 0;
155 : }
156 1 : if (mpc->spec != 0x01 && mpc->spec != 0x04) {
157 0 : pr_err("MPTABLE: bad table version (%d)!!\n", mpc->spec);
158 0 : return 0;
159 : }
160 1 : if (!mpc->lapic) {
161 0 : pr_err("MPTABLE: null local APIC address!\n");
162 0 : return 0;
163 : }
164 1 : memcpy(oem, mpc->oem, 8);
165 1 : oem[8] = 0;
166 1 : pr_info("MPTABLE: OEM ID: %s\n", oem);
167 :
168 1 : memcpy(str, mpc->productid, 12);
169 1 : str[12] = 0;
170 :
171 1 : pr_info("MPTABLE: Product ID: %s\n", str);
172 :
173 1 : pr_info("MPTABLE: APIC at: 0x%X\n", mpc->lapic);
174 :
175 1 : return 1;
176 : }
177 :
178 23 : static void skip_entry(unsigned char **ptr, int *count, int size)
179 : {
180 23 : *ptr += size;
181 23 : *count += size;
182 23 : }
183 :
184 0 : static void __init smp_dump_mptable(struct mpc_table *mpc, unsigned char *mpt)
185 : {
186 0 : pr_err("Your mptable is wrong, contact your HW vendor!\n");
187 0 : pr_cont("type %x\n", *mpt);
188 0 : print_hex_dump(KERN_ERR, " ", DUMP_PREFIX_ADDRESS, 16,
189 0 : 1, mpc, mpc->length, 1);
190 0 : }
191 :
192 1 : static int __init smp_read_mpc(struct mpc_table *mpc, unsigned early)
193 : {
194 1 : char str[16];
195 1 : char oem[10];
196 :
197 1 : int count = sizeof(*mpc);
198 1 : unsigned char *mpt = ((unsigned char *)mpc) + count;
199 :
200 1 : if (!smp_check_mpc(mpc, oem, str))
201 : return 0;
202 :
203 : /* Initialize the lapic mapping */
204 1 : if (!acpi_lapic)
205 1 : register_lapic_address(mpc->lapic);
206 :
207 1 : if (early)
208 : return 1;
209 :
210 : /* Now process the configuration blocks. */
211 24 : while (count < mpc->length) {
212 23 : switch (*mpt) {
213 : case MP_PROCESSOR:
214 : /* ACPI may have already provided this data */
215 4 : if (!acpi_lapic)
216 4 : MP_processor_info((struct mpc_cpu *)mpt);
217 4 : skip_entry(&mpt, &count, sizeof(struct mpc_cpu));
218 : break;
219 1 : case MP_BUS:
220 1 : MP_bus_info((struct mpc_bus *)mpt);
221 1 : skip_entry(&mpt, &count, sizeof(struct mpc_bus));
222 : break;
223 1 : case MP_IOAPIC:
224 1 : MP_ioapic_info((struct mpc_ioapic *)mpt);
225 1 : skip_entry(&mpt, &count, sizeof(struct mpc_ioapic));
226 : break;
227 15 : case MP_INTSRC:
228 15 : mp_save_irq((struct mpc_intsrc *)mpt);
229 15 : skip_entry(&mpt, &count, sizeof(struct mpc_intsrc));
230 : break;
231 2 : case MP_LINTSRC:
232 2 : MP_lintsrc_info((struct mpc_lintsrc *)mpt);
233 26 : skip_entry(&mpt, &count, sizeof(struct mpc_lintsrc));
234 : break;
235 0 : default:
236 : /* wrong mptable */
237 0 : smp_dump_mptable(mpc, mpt);
238 0 : count = mpc->length;
239 0 : break;
240 : }
241 : }
242 :
243 1 : if (!num_processors)
244 0 : pr_err("MPTABLE: no processors registered!\n");
245 1 : return num_processors;
246 : }
247 :
248 : #ifdef CONFIG_X86_IO_APIC
249 :
250 0 : static int __init ELCR_trigger(unsigned int irq)
251 : {
252 0 : unsigned int port;
253 :
254 0 : port = 0x4d0 + (irq >> 3);
255 0 : return (inb(port) >> (irq & 7)) & 1;
256 : }
257 :
258 0 : static void __init construct_default_ioirq_mptable(int mpc_default_type)
259 : {
260 0 : struct mpc_intsrc intsrc;
261 0 : int i;
262 0 : int ELCR_fallback = 0;
263 :
264 0 : intsrc.type = MP_INTSRC;
265 0 : intsrc.irqflag = MP_IRQTRIG_DEFAULT | MP_IRQPOL_DEFAULT;
266 0 : intsrc.srcbus = 0;
267 0 : intsrc.dstapic = mpc_ioapic_id(0);
268 :
269 0 : intsrc.irqtype = mp_INT;
270 :
271 : /*
272 : * If true, we have an ISA/PCI system with no IRQ entries
273 : * in the MP table. To prevent the PCI interrupts from being set up
274 : * incorrectly, we try to use the ELCR. The sanity check to see if
275 : * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
276 : * never be level sensitive, so we simply see if the ELCR agrees.
277 : * If it does, we assume it's valid.
278 : */
279 0 : if (mpc_default_type == 5) {
280 0 : pr_info("ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
281 :
282 0 : if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) ||
283 0 : ELCR_trigger(13))
284 0 : pr_err("ELCR contains invalid data... not using ELCR\n");
285 : else {
286 0 : pr_info("Using ELCR to identify PCI interrupts\n");
287 0 : ELCR_fallback = 1;
288 : }
289 : }
290 :
291 0 : for (i = 0; i < 16; i++) {
292 0 : switch (mpc_default_type) {
293 0 : case 2:
294 0 : if (i == 0 || i == 13)
295 0 : continue; /* IRQ0 & IRQ13 not connected */
296 0 : fallthrough;
297 : default:
298 0 : if (i == 2)
299 0 : continue; /* IRQ2 is never connected */
300 : }
301 :
302 0 : if (ELCR_fallback) {
303 : /*
304 : * If the ELCR indicates a level-sensitive interrupt, we
305 : * copy that information over to the MP table in the
306 : * irqflag field (level sensitive, active high polarity).
307 : */
308 0 : if (ELCR_trigger(i)) {
309 0 : intsrc.irqflag = MP_IRQTRIG_LEVEL |
310 : MP_IRQPOL_ACTIVE_HIGH;
311 : } else {
312 0 : intsrc.irqflag = MP_IRQTRIG_DEFAULT |
313 : MP_IRQPOL_DEFAULT;
314 : }
315 : }
316 :
317 0 : intsrc.srcbusirq = i;
318 0 : intsrc.dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
319 0 : mp_save_irq(&intsrc);
320 : }
321 :
322 0 : intsrc.irqtype = mp_ExtINT;
323 0 : intsrc.srcbusirq = 0;
324 0 : intsrc.dstirq = 0; /* 8259A to INTIN0 */
325 0 : mp_save_irq(&intsrc);
326 0 : }
327 :
328 :
329 0 : static void __init construct_ioapic_table(int mpc_default_type)
330 : {
331 0 : struct mpc_ioapic ioapic;
332 0 : struct mpc_bus bus;
333 :
334 0 : bus.type = MP_BUS;
335 0 : bus.busid = 0;
336 0 : switch (mpc_default_type) {
337 0 : default:
338 0 : pr_err("???\nUnknown standard configuration %d\n",
339 : mpc_default_type);
340 0 : fallthrough;
341 0 : case 1:
342 : case 5:
343 0 : memcpy(bus.bustype, "ISA ", 6);
344 0 : break;
345 0 : case 2:
346 : case 6:
347 : case 3:
348 0 : memcpy(bus.bustype, "EISA ", 6);
349 0 : break;
350 : }
351 0 : MP_bus_info(&bus);
352 0 : if (mpc_default_type > 4) {
353 0 : bus.busid = 1;
354 0 : memcpy(bus.bustype, "PCI ", 6);
355 0 : MP_bus_info(&bus);
356 : }
357 :
358 0 : ioapic.type = MP_IOAPIC;
359 0 : ioapic.apicid = 2;
360 0 : ioapic.apicver = mpc_default_type > 4 ? 0x10 : 0x01;
361 0 : ioapic.flags = MPC_APIC_USABLE;
362 0 : ioapic.apicaddr = IO_APIC_DEFAULT_PHYS_BASE;
363 0 : MP_ioapic_info(&ioapic);
364 :
365 : /*
366 : * We set up most of the low 16 IO-APIC pins according to MPS rules.
367 : */
368 0 : construct_default_ioirq_mptable(mpc_default_type);
369 0 : }
370 : #else
371 : static inline void __init construct_ioapic_table(int mpc_default_type) { }
372 : #endif
373 :
374 0 : static inline void __init construct_default_ISA_mptable(int mpc_default_type)
375 : {
376 0 : struct mpc_cpu processor;
377 0 : struct mpc_lintsrc lintsrc;
378 0 : int linttypes[2] = { mp_ExtINT, mp_NMI };
379 0 : int i;
380 :
381 : /*
382 : * local APIC has default address
383 : */
384 0 : mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
385 :
386 : /*
387 : * 2 CPUs, numbered 0 & 1.
388 : */
389 0 : processor.type = MP_PROCESSOR;
390 : /* Either an integrated APIC or a discrete 82489DX. */
391 0 : processor.apicver = mpc_default_type > 4 ? 0x10 : 0x01;
392 0 : processor.cpuflag = CPU_ENABLED;
393 0 : processor.cpufeature = (boot_cpu_data.x86 << 8) |
394 0 : (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_stepping;
395 0 : processor.featureflag = boot_cpu_data.x86_capability[CPUID_1_EDX];
396 0 : processor.reserved[0] = 0;
397 0 : processor.reserved[1] = 0;
398 0 : for (i = 0; i < 2; i++) {
399 0 : processor.apicid = i;
400 0 : MP_processor_info(&processor);
401 : }
402 :
403 0 : construct_ioapic_table(mpc_default_type);
404 :
405 0 : lintsrc.type = MP_LINTSRC;
406 0 : lintsrc.irqflag = MP_IRQTRIG_DEFAULT | MP_IRQPOL_DEFAULT;
407 0 : lintsrc.srcbusid = 0;
408 0 : lintsrc.srcbusirq = 0;
409 0 : lintsrc.destapic = MP_APIC_ALL;
410 0 : for (i = 0; i < 2; i++) {
411 0 : lintsrc.irqtype = linttypes[i];
412 0 : lintsrc.destapiclint = i;
413 0 : MP_lintsrc_info(&lintsrc);
414 : }
415 0 : }
416 :
417 : static unsigned long mpf_base;
418 : static bool mpf_found;
419 :
420 2 : static unsigned long __init get_mpc_size(unsigned long physptr)
421 : {
422 2 : struct mpc_table *mpc;
423 2 : unsigned long size;
424 :
425 2 : mpc = early_memremap(physptr, PAGE_SIZE);
426 2 : size = mpc->length;
427 2 : early_memunmap(mpc, PAGE_SIZE);
428 2 : apic_printk(APIC_VERBOSE, " mpc: %lx-%lx\n", physptr, physptr + size);
429 :
430 2 : return size;
431 : }
432 :
433 1 : static int __init check_physptr(struct mpf_intel *mpf, unsigned int early)
434 : {
435 1 : struct mpc_table *mpc;
436 1 : unsigned long size;
437 :
438 1 : size = get_mpc_size(mpf->physptr);
439 1 : mpc = early_memremap(mpf->physptr, size);
440 :
441 : /*
442 : * Read the physical hardware table. Anything here will
443 : * override the defaults.
444 : */
445 1 : if (!smp_read_mpc(mpc, early)) {
446 : #ifdef CONFIG_X86_LOCAL_APIC
447 0 : smp_found_config = 0;
448 : #endif
449 0 : pr_err("BIOS bug, MP table errors detected!...\n");
450 0 : pr_cont("... disabling SMP support. (tell your hw vendor)\n");
451 0 : early_memunmap(mpc, size);
452 0 : return -1;
453 : }
454 1 : early_memunmap(mpc, size);
455 :
456 1 : if (early)
457 : return -1;
458 :
459 : #ifdef CONFIG_X86_IO_APIC
460 : /*
461 : * If there are no explicit MP IRQ entries, then we are
462 : * broken. We set up most of the low 16 IO-APIC pins to
463 : * ISA defaults and hope it will work.
464 : */
465 1 : if (!mp_irq_entries) {
466 0 : struct mpc_bus bus;
467 :
468 0 : pr_err("BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
469 :
470 0 : bus.type = MP_BUS;
471 0 : bus.busid = 0;
472 0 : memcpy(bus.bustype, "ISA ", 6);
473 0 : MP_bus_info(&bus);
474 :
475 0 : construct_default_ioirq_mptable(0);
476 : }
477 : #endif
478 :
479 : return 0;
480 : }
481 :
482 : /*
483 : * Scan the memory blocks for an SMP configuration block.
484 : */
485 1 : void __init default_get_smp_config(unsigned int early)
486 : {
487 1 : struct mpf_intel *mpf;
488 :
489 1 : if (!smp_found_config)
490 : return;
491 :
492 1 : if (!mpf_found)
493 : return;
494 :
495 1 : if (acpi_lapic && early)
496 : return;
497 :
498 : /*
499 : * MPS doesn't support hyperthreading, aka only have
500 : * thread 0 apic id in MPS table
501 : */
502 1 : if (acpi_lapic && acpi_ioapic)
503 : return;
504 :
505 1 : mpf = early_memremap(mpf_base, sizeof(*mpf));
506 1 : if (!mpf) {
507 0 : pr_err("MPTABLE: error mapping MP table\n");
508 0 : return;
509 : }
510 :
511 1 : pr_info("Intel MultiProcessor Specification v1.%d\n",
512 : mpf->specification);
513 : #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
514 : if (mpf->feature2 & (1 << 7)) {
515 : pr_info(" IMCR and PIC compatibility mode.\n");
516 : pic_mode = 1;
517 : } else {
518 : pr_info(" Virtual Wire compatibility mode.\n");
519 : pic_mode = 0;
520 : }
521 : #endif
522 : /*
523 : * Now see if we need to read further.
524 : */
525 1 : if (mpf->feature1) {
526 0 : if (early) {
527 : /*
528 : * local APIC has default address
529 : */
530 0 : mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
531 0 : goto out;
532 : }
533 :
534 0 : pr_info("Default MP configuration #%d\n", mpf->feature1);
535 0 : construct_default_ISA_mptable(mpf->feature1);
536 :
537 1 : } else if (mpf->physptr) {
538 1 : if (check_physptr(mpf, early))
539 0 : goto out;
540 : } else
541 0 : BUG();
542 :
543 1 : if (!early)
544 1 : pr_info("Processors: %d\n", num_processors);
545 : /*
546 : * Only use the first configuration found.
547 : */
548 0 : out:
549 1 : early_memunmap(mpf, sizeof(*mpf));
550 : }
551 :
552 1 : static void __init smp_reserve_memory(struct mpf_intel *mpf)
553 : {
554 1 : memblock_reserve(mpf->physptr, get_mpc_size(mpf->physptr));
555 1 : }
556 :
557 2 : static int __init smp_scan_config(unsigned long base, unsigned long length)
558 : {
559 2 : unsigned int *bp;
560 2 : struct mpf_intel *mpf;
561 2 : int ret = 0;
562 :
563 2 : apic_printk(APIC_VERBOSE, "Scan for SMP in [mem %#010lx-%#010lx]\n",
564 : base, base + length - 1);
565 : BUILD_BUG_ON(sizeof(*mpf) != 16);
566 :
567 66 : while (length > 0) {
568 65 : bp = early_memremap(base, length);
569 65 : mpf = (struct mpf_intel *)bp;
570 65 : if ((*bp == SMP_MAGIC_IDENT) &&
571 1 : (mpf->length == 1) &&
572 1 : !mpf_checksum((unsigned char *)bp, 16) &&
573 1 : ((mpf->specification == 1)
574 1 : || (mpf->specification == 4))) {
575 : #ifdef CONFIG_X86_LOCAL_APIC
576 1 : smp_found_config = 1;
577 : #endif
578 1 : mpf_base = base;
579 1 : mpf_found = true;
580 :
581 1 : pr_info("found SMP MP-table at [mem %#010lx-%#010lx]\n",
582 : base, base + sizeof(*mpf) - 1);
583 :
584 1 : memblock_reserve(base, sizeof(*mpf));
585 1 : if (mpf->physptr)
586 1 : smp_reserve_memory(mpf);
587 :
588 : ret = 1;
589 : }
590 65 : early_memunmap(bp, length);
591 :
592 65 : if (ret)
593 : break;
594 :
595 64 : base += 16;
596 64 : length -= 16;
597 : }
598 2 : return ret;
599 : }
600 :
601 1 : void __init default_find_smp_config(void)
602 : {
603 1 : unsigned int address;
604 :
605 : /*
606 : * FIXME: Linux assumes you have 640K of base ram..
607 : * this continues the error...
608 : *
609 : * 1) Scan the bottom 1K for a signature
610 : * 2) Scan the top 1K of base RAM
611 : * 3) Scan the 64K of bios
612 : */
613 2 : if (smp_scan_config(0x0, 0x400) ||
614 1 : smp_scan_config(639 * 0x400, 0x400) ||
615 0 : smp_scan_config(0xF0000, 0x10000))
616 1 : return;
617 : /*
618 : * If it is an SMP machine we should know now, unless the
619 : * configuration is in an EISA bus machine with an
620 : * extended bios data area.
621 : *
622 : * there is a real-mode segmented pointer pointing to the
623 : * 4K EBDA area at 0x40E, calculate and scan it here.
624 : *
625 : * NOTE! There are Linux loaders that will corrupt the EBDA
626 : * area, and as such this kind of SMP config may be less
627 : * trustworthy, simply because the SMP table may have been
628 : * stomped on during early boot. These loaders are buggy and
629 : * should be fixed.
630 : *
631 : * MP1.4 SPEC states to only scan first 1K of 4K EBDA.
632 : */
633 :
634 0 : address = get_bios_ebda();
635 0 : if (address)
636 0 : smp_scan_config(address, 0x400);
637 : }
638 :
639 : #ifdef CONFIG_X86_IO_APIC
640 : static u8 __initdata irq_used[MAX_IRQ_SOURCES];
641 :
642 0 : static int __init get_MP_intsrc_index(struct mpc_intsrc *m)
643 : {
644 0 : int i;
645 :
646 0 : if (m->irqtype != mp_INT)
647 : return 0;
648 :
649 0 : if (m->irqflag != (MP_IRQTRIG_LEVEL | MP_IRQPOL_ACTIVE_LOW))
650 : return 0;
651 :
652 : /* not legacy */
653 :
654 0 : for (i = 0; i < mp_irq_entries; i++) {
655 0 : if (mp_irqs[i].irqtype != mp_INT)
656 0 : continue;
657 :
658 0 : if (mp_irqs[i].irqflag != (MP_IRQTRIG_LEVEL |
659 : MP_IRQPOL_ACTIVE_LOW))
660 0 : continue;
661 :
662 0 : if (mp_irqs[i].srcbus != m->srcbus)
663 0 : continue;
664 0 : if (mp_irqs[i].srcbusirq != m->srcbusirq)
665 0 : continue;
666 0 : if (irq_used[i]) {
667 : /* already claimed */
668 : return -2;
669 : }
670 0 : irq_used[i] = 1;
671 0 : return i;
672 : }
673 :
674 : /* not found */
675 : return -1;
676 : }
677 :
678 : #define SPARE_SLOT_NUM 20
679 :
680 : static struct mpc_intsrc __initdata *m_spare[SPARE_SLOT_NUM];
681 :
682 0 : static void __init check_irq_src(struct mpc_intsrc *m, int *nr_m_spare)
683 : {
684 0 : int i;
685 :
686 0 : apic_printk(APIC_VERBOSE, "OLD ");
687 0 : print_mp_irq_info(m);
688 :
689 0 : i = get_MP_intsrc_index(m);
690 0 : if (i > 0) {
691 0 : memcpy(m, &mp_irqs[i], sizeof(*m));
692 0 : apic_printk(APIC_VERBOSE, "NEW ");
693 0 : print_mp_irq_info(&mp_irqs[i]);
694 0 : return;
695 : }
696 0 : if (!i) {
697 : /* legacy, do nothing */
698 : return;
699 : }
700 0 : if (*nr_m_spare < SPARE_SLOT_NUM) {
701 : /*
702 : * not found (-1), or duplicated (-2) are invalid entries,
703 : * we need to use the slot later
704 : */
705 0 : m_spare[*nr_m_spare] = m;
706 0 : *nr_m_spare += 1;
707 : }
708 : }
709 :
710 : static int __init
711 0 : check_slot(unsigned long mpc_new_phys, unsigned long mpc_new_length, int count)
712 : {
713 0 : if (!mpc_new_phys || count <= mpc_new_length) {
714 0 : WARN(1, "update_mptable: No spare slots (length: %x)\n", count);
715 0 : return -1;
716 : }
717 :
718 : return 0;
719 : }
720 : #else /* CONFIG_X86_IO_APIC */
721 : static
722 : inline void __init check_irq_src(struct mpc_intsrc *m, int *nr_m_spare) {}
723 : #endif /* CONFIG_X86_IO_APIC */
724 :
725 0 : static int __init replace_intsrc_all(struct mpc_table *mpc,
726 : unsigned long mpc_new_phys,
727 : unsigned long mpc_new_length)
728 : {
729 : #ifdef CONFIG_X86_IO_APIC
730 0 : int i;
731 : #endif
732 0 : int count = sizeof(*mpc);
733 0 : int nr_m_spare = 0;
734 0 : unsigned char *mpt = ((unsigned char *)mpc) + count;
735 :
736 0 : pr_info("mpc_length %x\n", mpc->length);
737 0 : while (count < mpc->length) {
738 0 : switch (*mpt) {
739 : case MP_PROCESSOR:
740 0 : skip_entry(&mpt, &count, sizeof(struct mpc_cpu));
741 : break;
742 : case MP_BUS:
743 0 : skip_entry(&mpt, &count, sizeof(struct mpc_bus));
744 : break;
745 : case MP_IOAPIC:
746 0 : skip_entry(&mpt, &count, sizeof(struct mpc_ioapic));
747 : break;
748 0 : case MP_INTSRC:
749 0 : check_irq_src((struct mpc_intsrc *)mpt, &nr_m_spare);
750 0 : skip_entry(&mpt, &count, sizeof(struct mpc_intsrc));
751 : break;
752 : case MP_LINTSRC:
753 0 : skip_entry(&mpt, &count, sizeof(struct mpc_lintsrc));
754 : break;
755 0 : default:
756 : /* wrong mptable */
757 0 : smp_dump_mptable(mpc, mpt);
758 0 : goto out;
759 : }
760 : }
761 :
762 : #ifdef CONFIG_X86_IO_APIC
763 0 : for (i = 0; i < mp_irq_entries; i++) {
764 0 : if (irq_used[i])
765 0 : continue;
766 :
767 0 : if (mp_irqs[i].irqtype != mp_INT)
768 0 : continue;
769 :
770 0 : if (mp_irqs[i].irqflag != (MP_IRQTRIG_LEVEL |
771 : MP_IRQPOL_ACTIVE_LOW))
772 0 : continue;
773 :
774 0 : if (nr_m_spare > 0) {
775 0 : apic_printk(APIC_VERBOSE, "*NEW* found\n");
776 0 : nr_m_spare--;
777 0 : memcpy(m_spare[nr_m_spare], &mp_irqs[i], sizeof(mp_irqs[i]));
778 0 : m_spare[nr_m_spare] = NULL;
779 : } else {
780 0 : struct mpc_intsrc *m = (struct mpc_intsrc *)mpt;
781 0 : count += sizeof(struct mpc_intsrc);
782 0 : if (check_slot(mpc_new_phys, mpc_new_length, count) < 0)
783 0 : goto out;
784 0 : memcpy(m, &mp_irqs[i], sizeof(*m));
785 0 : mpc->length = count;
786 0 : mpt += sizeof(struct mpc_intsrc);
787 : }
788 0 : print_mp_irq_info(&mp_irqs[i]);
789 : }
790 : #endif
791 0 : out:
792 : /* update checksum */
793 0 : mpc->checksum = 0;
794 0 : mpc->checksum -= mpf_checksum((unsigned char *)mpc, mpc->length);
795 :
796 0 : return 0;
797 : }
798 :
799 : int enable_update_mptable;
800 :
801 0 : static int __init update_mptable_setup(char *str)
802 : {
803 0 : enable_update_mptable = 1;
804 : #ifdef CONFIG_PCI
805 : pci_routeirq = 1;
806 : #endif
807 0 : return 0;
808 : }
809 : early_param("update_mptable", update_mptable_setup);
810 :
811 : static unsigned long __initdata mpc_new_phys;
812 : static unsigned long mpc_new_length __initdata = 4096;
813 :
814 : /* alloc_mptable or alloc_mptable=4k */
815 : static int __initdata alloc_mptable;
816 0 : static int __init parse_alloc_mptable_opt(char *p)
817 : {
818 0 : enable_update_mptable = 1;
819 : #ifdef CONFIG_PCI
820 : pci_routeirq = 1;
821 : #endif
822 0 : alloc_mptable = 1;
823 0 : if (!p)
824 : return 0;
825 0 : mpc_new_length = memparse(p, &p);
826 0 : return 0;
827 : }
828 : early_param("alloc_mptable", parse_alloc_mptable_opt);
829 :
830 1 : void __init e820__memblock_alloc_reserved_mpc_new(void)
831 : {
832 1 : if (enable_update_mptable && alloc_mptable)
833 0 : mpc_new_phys = e820__memblock_alloc_reserved(mpc_new_length, 4);
834 1 : }
835 :
836 1 : static int __init update_mp_table(void)
837 : {
838 1 : char str[16];
839 1 : char oem[10];
840 1 : struct mpf_intel *mpf;
841 1 : struct mpc_table *mpc, *mpc_new;
842 1 : unsigned long size;
843 :
844 1 : if (!enable_update_mptable)
845 : return 0;
846 :
847 0 : if (!mpf_found)
848 : return 0;
849 :
850 0 : mpf = early_memremap(mpf_base, sizeof(*mpf));
851 0 : if (!mpf) {
852 0 : pr_err("MPTABLE: mpf early_memremap() failed\n");
853 0 : return 0;
854 : }
855 :
856 : /*
857 : * Now see if we need to go further.
858 : */
859 0 : if (mpf->feature1)
860 0 : goto do_unmap_mpf;
861 :
862 0 : if (!mpf->physptr)
863 0 : goto do_unmap_mpf;
864 :
865 0 : size = get_mpc_size(mpf->physptr);
866 0 : mpc = early_memremap(mpf->physptr, size);
867 0 : if (!mpc) {
868 0 : pr_err("MPTABLE: mpc early_memremap() failed\n");
869 0 : goto do_unmap_mpf;
870 : }
871 :
872 0 : if (!smp_check_mpc(mpc, oem, str))
873 0 : goto do_unmap_mpc;
874 :
875 0 : pr_info("mpf: %llx\n", (u64)mpf_base);
876 0 : pr_info("physptr: %x\n", mpf->physptr);
877 :
878 0 : if (mpc_new_phys && mpc->length > mpc_new_length) {
879 0 : mpc_new_phys = 0;
880 0 : pr_info("mpc_new_length is %ld, please use alloc_mptable=8k\n",
881 : mpc_new_length);
882 : }
883 :
884 0 : if (!mpc_new_phys) {
885 0 : unsigned char old, new;
886 : /* check if we can change the position */
887 0 : mpc->checksum = 0;
888 0 : old = mpf_checksum((unsigned char *)mpc, mpc->length);
889 0 : mpc->checksum = 0xff;
890 0 : new = mpf_checksum((unsigned char *)mpc, mpc->length);
891 0 : if (old == new) {
892 0 : pr_info("mpc is readonly, please try alloc_mptable instead\n");
893 0 : goto do_unmap_mpc;
894 : }
895 0 : pr_info("use in-position replacing\n");
896 : } else {
897 0 : mpc_new = early_memremap(mpc_new_phys, mpc_new_length);
898 0 : if (!mpc_new) {
899 0 : pr_err("MPTABLE: new mpc early_memremap() failed\n");
900 0 : goto do_unmap_mpc;
901 : }
902 0 : mpf->physptr = mpc_new_phys;
903 0 : memcpy(mpc_new, mpc, mpc->length);
904 0 : early_memunmap(mpc, size);
905 0 : mpc = mpc_new;
906 0 : size = mpc_new_length;
907 : /* check if we can modify that */
908 0 : if (mpc_new_phys - mpf->physptr) {
909 0 : struct mpf_intel *mpf_new;
910 : /* steal 16 bytes from [0, 1k) */
911 0 : mpf_new = early_memremap(0x400 - 16, sizeof(*mpf_new));
912 0 : if (!mpf_new) {
913 0 : pr_err("MPTABLE: new mpf early_memremap() failed\n");
914 0 : goto do_unmap_mpc;
915 : }
916 0 : pr_info("mpf new: %x\n", 0x400 - 16);
917 0 : memcpy(mpf_new, mpf, 16);
918 0 : early_memunmap(mpf, sizeof(*mpf));
919 0 : mpf = mpf_new;
920 0 : mpf->physptr = mpc_new_phys;
921 : }
922 0 : mpf->checksum = 0;
923 0 : mpf->checksum -= mpf_checksum((unsigned char *)mpf, 16);
924 0 : pr_info("physptr new: %x\n", mpf->physptr);
925 : }
926 :
927 : /*
928 : * only replace the one with mp_INT and
929 : * MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
930 : * already in mp_irqs , stored by ... and mp_config_acpi_gsi,
931 : * may need pci=routeirq for all coverage
932 : */
933 0 : replace_intsrc_all(mpc, mpc_new_phys, mpc_new_length);
934 :
935 0 : do_unmap_mpc:
936 0 : early_memunmap(mpc, size);
937 :
938 0 : do_unmap_mpf:
939 0 : early_memunmap(mpf, sizeof(*mpf));
940 :
941 0 : return 0;
942 : }
943 :
944 : late_initcall(update_mp_table);
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