Line data Source code
1 : // SPDX-License-Identifier: GPL-2.0+
2 : /*
3 : * Base port operations for 8250/16550-type serial ports
4 : *
5 : * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 : * Split from 8250_core.c, Copyright (C) 2001 Russell King.
7 : *
8 : * A note about mapbase / membase
9 : *
10 : * mapbase is the physical address of the IO port.
11 : * membase is an 'ioremapped' cookie.
12 : */
13 :
14 : #include <linux/module.h>
15 : #include <linux/moduleparam.h>
16 : #include <linux/ioport.h>
17 : #include <linux/init.h>
18 : #include <linux/console.h>
19 : #include <linux/gpio/consumer.h>
20 : #include <linux/sysrq.h>
21 : #include <linux/delay.h>
22 : #include <linux/platform_device.h>
23 : #include <linux/tty.h>
24 : #include <linux/ratelimit.h>
25 : #include <linux/tty_flip.h>
26 : #include <linux/serial.h>
27 : #include <linux/serial_8250.h>
28 : #include <linux/nmi.h>
29 : #include <linux/mutex.h>
30 : #include <linux/slab.h>
31 : #include <linux/uaccess.h>
32 : #include <linux/pm_runtime.h>
33 : #include <linux/ktime.h>
34 :
35 : #include <asm/io.h>
36 : #include <asm/irq.h>
37 :
38 : #include "8250.h"
39 :
40 : /* Nuvoton NPCM timeout register */
41 : #define UART_NPCM_TOR 7
42 : #define UART_NPCM_TOIE BIT(7) /* Timeout Interrupt Enable */
43 :
44 : /*
45 : * Debugging.
46 : */
47 : #if 0
48 : #define DEBUG_AUTOCONF(fmt...) printk(fmt)
49 : #else
50 : #define DEBUG_AUTOCONF(fmt...) do { } while (0)
51 : #endif
52 :
53 : #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
54 :
55 : /*
56 : * Here we define the default xmit fifo size used for each type of UART.
57 : */
58 : static const struct serial8250_config uart_config[] = {
59 : [PORT_UNKNOWN] = {
60 : .name = "unknown",
61 : .fifo_size = 1,
62 : .tx_loadsz = 1,
63 : },
64 : [PORT_8250] = {
65 : .name = "8250",
66 : .fifo_size = 1,
67 : .tx_loadsz = 1,
68 : },
69 : [PORT_16450] = {
70 : .name = "16450",
71 : .fifo_size = 1,
72 : .tx_loadsz = 1,
73 : },
74 : [PORT_16550] = {
75 : .name = "16550",
76 : .fifo_size = 1,
77 : .tx_loadsz = 1,
78 : },
79 : [PORT_16550A] = {
80 : .name = "16550A",
81 : .fifo_size = 16,
82 : .tx_loadsz = 16,
83 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
84 : .rxtrig_bytes = {1, 4, 8, 14},
85 : .flags = UART_CAP_FIFO,
86 : },
87 : [PORT_CIRRUS] = {
88 : .name = "Cirrus",
89 : .fifo_size = 1,
90 : .tx_loadsz = 1,
91 : },
92 : [PORT_16650] = {
93 : .name = "ST16650",
94 : .fifo_size = 1,
95 : .tx_loadsz = 1,
96 : .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
97 : },
98 : [PORT_16650V2] = {
99 : .name = "ST16650V2",
100 : .fifo_size = 32,
101 : .tx_loadsz = 16,
102 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
103 : UART_FCR_T_TRIG_00,
104 : .rxtrig_bytes = {8, 16, 24, 28},
105 : .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
106 : },
107 : [PORT_16750] = {
108 : .name = "TI16750",
109 : .fifo_size = 64,
110 : .tx_loadsz = 64,
111 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
112 : UART_FCR7_64BYTE,
113 : .rxtrig_bytes = {1, 16, 32, 56},
114 : .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
115 : },
116 : [PORT_STARTECH] = {
117 : .name = "Startech",
118 : .fifo_size = 1,
119 : .tx_loadsz = 1,
120 : },
121 : [PORT_16C950] = {
122 : .name = "16C950/954",
123 : .fifo_size = 128,
124 : .tx_loadsz = 128,
125 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
126 : /* UART_CAP_EFR breaks billionon CF bluetooth card. */
127 : .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
128 : },
129 : [PORT_16654] = {
130 : .name = "ST16654",
131 : .fifo_size = 64,
132 : .tx_loadsz = 32,
133 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
134 : UART_FCR_T_TRIG_10,
135 : .rxtrig_bytes = {8, 16, 56, 60},
136 : .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
137 : },
138 : [PORT_16850] = {
139 : .name = "XR16850",
140 : .fifo_size = 128,
141 : .tx_loadsz = 128,
142 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
143 : .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
144 : },
145 : [PORT_RSA] = {
146 : .name = "RSA",
147 : .fifo_size = 2048,
148 : .tx_loadsz = 2048,
149 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
150 : .flags = UART_CAP_FIFO,
151 : },
152 : [PORT_NS16550A] = {
153 : .name = "NS16550A",
154 : .fifo_size = 16,
155 : .tx_loadsz = 16,
156 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
157 : .flags = UART_CAP_FIFO | UART_NATSEMI,
158 : },
159 : [PORT_XSCALE] = {
160 : .name = "XScale",
161 : .fifo_size = 32,
162 : .tx_loadsz = 32,
163 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
164 : .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
165 : },
166 : [PORT_OCTEON] = {
167 : .name = "OCTEON",
168 : .fifo_size = 64,
169 : .tx_loadsz = 64,
170 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
171 : .flags = UART_CAP_FIFO,
172 : },
173 : [PORT_AR7] = {
174 : .name = "AR7",
175 : .fifo_size = 16,
176 : .tx_loadsz = 16,
177 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
178 : .flags = UART_CAP_FIFO /* | UART_CAP_AFE */,
179 : },
180 : [PORT_U6_16550A] = {
181 : .name = "U6_16550A",
182 : .fifo_size = 64,
183 : .tx_loadsz = 64,
184 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
185 : .flags = UART_CAP_FIFO | UART_CAP_AFE,
186 : },
187 : [PORT_TEGRA] = {
188 : .name = "Tegra",
189 : .fifo_size = 32,
190 : .tx_loadsz = 8,
191 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
192 : UART_FCR_T_TRIG_01,
193 : .rxtrig_bytes = {1, 4, 8, 14},
194 : .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
195 : },
196 : [PORT_XR17D15X] = {
197 : .name = "XR17D15X",
198 : .fifo_size = 64,
199 : .tx_loadsz = 64,
200 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
201 : .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
202 : UART_CAP_SLEEP,
203 : },
204 : [PORT_XR17V35X] = {
205 : .name = "XR17V35X",
206 : .fifo_size = 256,
207 : .tx_loadsz = 256,
208 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
209 : UART_FCR_T_TRIG_11,
210 : .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
211 : UART_CAP_SLEEP,
212 : },
213 : [PORT_LPC3220] = {
214 : .name = "LPC3220",
215 : .fifo_size = 64,
216 : .tx_loadsz = 32,
217 : .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
218 : UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
219 : .flags = UART_CAP_FIFO,
220 : },
221 : [PORT_BRCM_TRUMANAGE] = {
222 : .name = "TruManage",
223 : .fifo_size = 1,
224 : .tx_loadsz = 1024,
225 : .flags = UART_CAP_HFIFO,
226 : },
227 : [PORT_8250_CIR] = {
228 : .name = "CIR port"
229 : },
230 : [PORT_ALTR_16550_F32] = {
231 : .name = "Altera 16550 FIFO32",
232 : .fifo_size = 32,
233 : .tx_loadsz = 32,
234 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
235 : .rxtrig_bytes = {1, 8, 16, 30},
236 : .flags = UART_CAP_FIFO | UART_CAP_AFE,
237 : },
238 : [PORT_ALTR_16550_F64] = {
239 : .name = "Altera 16550 FIFO64",
240 : .fifo_size = 64,
241 : .tx_loadsz = 64,
242 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
243 : .rxtrig_bytes = {1, 16, 32, 62},
244 : .flags = UART_CAP_FIFO | UART_CAP_AFE,
245 : },
246 : [PORT_ALTR_16550_F128] = {
247 : .name = "Altera 16550 FIFO128",
248 : .fifo_size = 128,
249 : .tx_loadsz = 128,
250 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
251 : .rxtrig_bytes = {1, 32, 64, 126},
252 : .flags = UART_CAP_FIFO | UART_CAP_AFE,
253 : },
254 : /*
255 : * tx_loadsz is set to 63-bytes instead of 64-bytes to implement
256 : * workaround of errata A-008006 which states that tx_loadsz should
257 : * be configured less than Maximum supported fifo bytes.
258 : */
259 : [PORT_16550A_FSL64] = {
260 : .name = "16550A_FSL64",
261 : .fifo_size = 64,
262 : .tx_loadsz = 63,
263 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
264 : UART_FCR7_64BYTE,
265 : .flags = UART_CAP_FIFO,
266 : },
267 : [PORT_RT2880] = {
268 : .name = "Palmchip BK-3103",
269 : .fifo_size = 16,
270 : .tx_loadsz = 16,
271 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
272 : .rxtrig_bytes = {1, 4, 8, 14},
273 : .flags = UART_CAP_FIFO,
274 : },
275 : [PORT_DA830] = {
276 : .name = "TI DA8xx/66AK2x",
277 : .fifo_size = 16,
278 : .tx_loadsz = 16,
279 : .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
280 : UART_FCR_R_TRIG_10,
281 : .rxtrig_bytes = {1, 4, 8, 14},
282 : .flags = UART_CAP_FIFO | UART_CAP_AFE,
283 : },
284 : [PORT_MTK_BTIF] = {
285 : .name = "MediaTek BTIF",
286 : .fifo_size = 16,
287 : .tx_loadsz = 16,
288 : .fcr = UART_FCR_ENABLE_FIFO |
289 : UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
290 : .flags = UART_CAP_FIFO,
291 : },
292 : [PORT_NPCM] = {
293 : .name = "Nuvoton 16550",
294 : .fifo_size = 16,
295 : .tx_loadsz = 16,
296 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
297 : UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
298 : .rxtrig_bytes = {1, 4, 8, 14},
299 : .flags = UART_CAP_FIFO,
300 : },
301 : [PORT_SUNIX] = {
302 : .name = "Sunix",
303 : .fifo_size = 128,
304 : .tx_loadsz = 128,
305 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
306 : .rxtrig_bytes = {1, 32, 64, 112},
307 : .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
308 : },
309 : };
310 :
311 : /* Uart divisor latch read */
312 0 : static int default_serial_dl_read(struct uart_8250_port *up)
313 : {
314 0 : return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;
315 : }
316 :
317 : /* Uart divisor latch write */
318 2 : static void default_serial_dl_write(struct uart_8250_port *up, int value)
319 : {
320 2 : serial_out(up, UART_DLL, value & 0xff);
321 2 : serial_out(up, UART_DLM, value >> 8 & 0xff);
322 2 : }
323 :
324 : #ifdef CONFIG_SERIAL_8250_RT288X
325 :
326 : /* Au1x00/RT288x UART hardware has a weird register layout */
327 : static const s8 au_io_in_map[8] = {
328 : 0, /* UART_RX */
329 : 2, /* UART_IER */
330 : 3, /* UART_IIR */
331 : 5, /* UART_LCR */
332 : 6, /* UART_MCR */
333 : 7, /* UART_LSR */
334 : 8, /* UART_MSR */
335 : -1, /* UART_SCR (unmapped) */
336 : };
337 :
338 : static const s8 au_io_out_map[8] = {
339 : 1, /* UART_TX */
340 : 2, /* UART_IER */
341 : 4, /* UART_FCR */
342 : 5, /* UART_LCR */
343 : 6, /* UART_MCR */
344 : -1, /* UART_LSR (unmapped) */
345 : -1, /* UART_MSR (unmapped) */
346 : -1, /* UART_SCR (unmapped) */
347 : };
348 :
349 : unsigned int au_serial_in(struct uart_port *p, int offset)
350 : {
351 : if (offset >= ARRAY_SIZE(au_io_in_map))
352 : return UINT_MAX;
353 : offset = au_io_in_map[offset];
354 : if (offset < 0)
355 : return UINT_MAX;
356 : return __raw_readl(p->membase + (offset << p->regshift));
357 : }
358 :
359 : void au_serial_out(struct uart_port *p, int offset, int value)
360 : {
361 : if (offset >= ARRAY_SIZE(au_io_out_map))
362 : return;
363 : offset = au_io_out_map[offset];
364 : if (offset < 0)
365 : return;
366 : __raw_writel(value, p->membase + (offset << p->regshift));
367 : }
368 :
369 : /* Au1x00 haven't got a standard divisor latch */
370 : static int au_serial_dl_read(struct uart_8250_port *up)
371 : {
372 : return __raw_readl(up->port.membase + 0x28);
373 : }
374 :
375 : static void au_serial_dl_write(struct uart_8250_port *up, int value)
376 : {
377 : __raw_writel(value, up->port.membase + 0x28);
378 : }
379 :
380 : #endif
381 :
382 0 : static unsigned int hub6_serial_in(struct uart_port *p, int offset)
383 : {
384 0 : offset = offset << p->regshift;
385 0 : outb(p->hub6 - 1 + offset, p->iobase);
386 0 : return inb(p->iobase + 1);
387 : }
388 :
389 0 : static void hub6_serial_out(struct uart_port *p, int offset, int value)
390 : {
391 0 : offset = offset << p->regshift;
392 0 : outb(p->hub6 - 1 + offset, p->iobase);
393 0 : outb(value, p->iobase + 1);
394 0 : }
395 :
396 0 : static unsigned int mem_serial_in(struct uart_port *p, int offset)
397 : {
398 0 : offset = offset << p->regshift;
399 0 : return readb(p->membase + offset);
400 : }
401 :
402 0 : static void mem_serial_out(struct uart_port *p, int offset, int value)
403 : {
404 0 : offset = offset << p->regshift;
405 0 : writeb(value, p->membase + offset);
406 0 : }
407 :
408 0 : static void mem16_serial_out(struct uart_port *p, int offset, int value)
409 : {
410 0 : offset = offset << p->regshift;
411 0 : writew(value, p->membase + offset);
412 0 : }
413 :
414 0 : static unsigned int mem16_serial_in(struct uart_port *p, int offset)
415 : {
416 0 : offset = offset << p->regshift;
417 0 : return readw(p->membase + offset);
418 : }
419 :
420 0 : static void mem32_serial_out(struct uart_port *p, int offset, int value)
421 : {
422 0 : offset = offset << p->regshift;
423 0 : writel(value, p->membase + offset);
424 0 : }
425 :
426 0 : static unsigned int mem32_serial_in(struct uart_port *p, int offset)
427 : {
428 0 : offset = offset << p->regshift;
429 0 : return readl(p->membase + offset);
430 : }
431 :
432 0 : static void mem32be_serial_out(struct uart_port *p, int offset, int value)
433 : {
434 0 : offset = offset << p->regshift;
435 0 : iowrite32be(value, p->membase + offset);
436 0 : }
437 :
438 0 : static unsigned int mem32be_serial_in(struct uart_port *p, int offset)
439 : {
440 0 : offset = offset << p->regshift;
441 0 : return ioread32be(p->membase + offset);
442 : }
443 :
444 16989 : static unsigned int io_serial_in(struct uart_port *p, int offset)
445 : {
446 16989 : offset = offset << p->regshift;
447 16989 : return inb(p->iobase + offset);
448 : }
449 :
450 24487 : static void io_serial_out(struct uart_port *p, int offset, int value)
451 : {
452 24487 : offset = offset << p->regshift;
453 24487 : outb(value, p->iobase + offset);
454 24487 : }
455 :
456 : static int serial8250_default_handle_irq(struct uart_port *port);
457 :
458 4 : static void set_io_from_upio(struct uart_port *p)
459 : {
460 4 : struct uart_8250_port *up = up_to_u8250p(p);
461 :
462 4 : up->dl_read = default_serial_dl_read;
463 4 : up->dl_write = default_serial_dl_write;
464 :
465 4 : switch (p->iotype) {
466 0 : case UPIO_HUB6:
467 0 : p->serial_in = hub6_serial_in;
468 0 : p->serial_out = hub6_serial_out;
469 0 : break;
470 :
471 0 : case UPIO_MEM:
472 0 : p->serial_in = mem_serial_in;
473 0 : p->serial_out = mem_serial_out;
474 0 : break;
475 :
476 0 : case UPIO_MEM16:
477 0 : p->serial_in = mem16_serial_in;
478 0 : p->serial_out = mem16_serial_out;
479 0 : break;
480 :
481 0 : case UPIO_MEM32:
482 0 : p->serial_in = mem32_serial_in;
483 0 : p->serial_out = mem32_serial_out;
484 0 : break;
485 :
486 0 : case UPIO_MEM32BE:
487 0 : p->serial_in = mem32be_serial_in;
488 0 : p->serial_out = mem32be_serial_out;
489 0 : break;
490 :
491 : #ifdef CONFIG_SERIAL_8250_RT288X
492 : case UPIO_AU:
493 : p->serial_in = au_serial_in;
494 : p->serial_out = au_serial_out;
495 : up->dl_read = au_serial_dl_read;
496 : up->dl_write = au_serial_dl_write;
497 : break;
498 : #endif
499 :
500 4 : default:
501 4 : p->serial_in = io_serial_in;
502 4 : p->serial_out = io_serial_out;
503 4 : break;
504 : }
505 : /* Remember loaded iotype */
506 4 : up->cur_iotype = p->iotype;
507 4 : p->handle_irq = serial8250_default_handle_irq;
508 4 : }
509 :
510 : static void
511 2 : serial_port_out_sync(struct uart_port *p, int offset, int value)
512 : {
513 2 : switch (p->iotype) {
514 0 : case UPIO_MEM:
515 : case UPIO_MEM16:
516 : case UPIO_MEM32:
517 : case UPIO_MEM32BE:
518 : case UPIO_AU:
519 0 : p->serial_out(p, offset, value);
520 0 : p->serial_in(p, UART_LCR); /* safe, no side-effects */
521 0 : break;
522 2 : default:
523 2 : p->serial_out(p, offset, value);
524 : }
525 2 : }
526 :
527 : /*
528 : * For the 16C950
529 : */
530 0 : static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
531 : {
532 0 : serial_out(up, UART_SCR, offset);
533 0 : serial_out(up, UART_ICR, value);
534 0 : }
535 :
536 : static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
537 : {
538 : unsigned int value;
539 :
540 : serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
541 : serial_out(up, UART_SCR, offset);
542 : value = serial_in(up, UART_ICR);
543 : serial_icr_write(up, UART_ACR, up->acr);
544 :
545 : return value;
546 : }
547 :
548 : /*
549 : * FIFO support.
550 : */
551 2 : static void serial8250_clear_fifos(struct uart_8250_port *p)
552 : {
553 2 : if (p->capabilities & UART_CAP_FIFO) {
554 2 : serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
555 2 : serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
556 : UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
557 2 : serial_out(p, UART_FCR, 0);
558 : }
559 2 : }
560 :
561 : static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t);
562 : static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t);
563 :
564 0 : void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
565 : {
566 0 : serial8250_clear_fifos(p);
567 0 : serial_out(p, UART_FCR, p->fcr);
568 0 : }
569 : EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
570 :
571 1268 : void serial8250_rpm_get(struct uart_8250_port *p)
572 : {
573 1268 : if (!(p->capabilities & UART_CAP_RPM))
574 : return;
575 1268 : pm_runtime_get_sync(p->port.dev);
576 : }
577 : EXPORT_SYMBOL_GPL(serial8250_rpm_get);
578 :
579 1268 : void serial8250_rpm_put(struct uart_8250_port *p)
580 : {
581 1268 : if (!(p->capabilities & UART_CAP_RPM))
582 : return;
583 1268 : pm_runtime_mark_last_busy(p->port.dev);
584 2 : pm_runtime_put_autosuspend(p->port.dev);
585 : }
586 : EXPORT_SYMBOL_GPL(serial8250_rpm_put);
587 :
588 : /**
589 : * serial8250_em485_init() - put uart_8250_port into rs485 emulating
590 : * @p: uart_8250_port port instance
591 : *
592 : * The function is used to start rs485 software emulating on the
593 : * &struct uart_8250_port* @p. Namely, RTS is switched before/after
594 : * transmission. The function is idempotent, so it is safe to call it
595 : * multiple times.
596 : *
597 : * The caller MUST enable interrupt on empty shift register before
598 : * calling serial8250_em485_init(). This interrupt is not a part of
599 : * 8250 standard, but implementation defined.
600 : *
601 : * The function is supposed to be called from .rs485_config callback
602 : * or from any other callback protected with p->port.lock spinlock.
603 : *
604 : * See also serial8250_em485_destroy()
605 : *
606 : * Return 0 - success, -errno - otherwise
607 : */
608 0 : static int serial8250_em485_init(struct uart_8250_port *p)
609 : {
610 0 : if (p->em485)
611 : return 0;
612 :
613 0 : p->em485 = kmalloc(sizeof(struct uart_8250_em485), GFP_ATOMIC);
614 0 : if (!p->em485)
615 : return -ENOMEM;
616 :
617 0 : hrtimer_init(&p->em485->stop_tx_timer, CLOCK_MONOTONIC,
618 : HRTIMER_MODE_REL);
619 0 : hrtimer_init(&p->em485->start_tx_timer, CLOCK_MONOTONIC,
620 : HRTIMER_MODE_REL);
621 0 : p->em485->stop_tx_timer.function = &serial8250_em485_handle_stop_tx;
622 0 : p->em485->start_tx_timer.function = &serial8250_em485_handle_start_tx;
623 0 : p->em485->port = p;
624 0 : p->em485->active_timer = NULL;
625 0 : p->em485->tx_stopped = true;
626 :
627 0 : p->rs485_stop_tx(p);
628 :
629 0 : return 0;
630 : }
631 :
632 : /**
633 : * serial8250_em485_destroy() - put uart_8250_port into normal state
634 : * @p: uart_8250_port port instance
635 : *
636 : * The function is used to stop rs485 software emulating on the
637 : * &struct uart_8250_port* @p. The function is idempotent, so it is safe to
638 : * call it multiple times.
639 : *
640 : * The function is supposed to be called from .rs485_config callback
641 : * or from any other callback protected with p->port.lock spinlock.
642 : *
643 : * See also serial8250_em485_init()
644 : */
645 0 : void serial8250_em485_destroy(struct uart_8250_port *p)
646 : {
647 0 : if (!p->em485)
648 : return;
649 :
650 0 : hrtimer_cancel(&p->em485->start_tx_timer);
651 0 : hrtimer_cancel(&p->em485->stop_tx_timer);
652 :
653 0 : kfree(p->em485);
654 0 : p->em485 = NULL;
655 : }
656 : EXPORT_SYMBOL_GPL(serial8250_em485_destroy);
657 :
658 : /**
659 : * serial8250_em485_config() - generic ->rs485_config() callback
660 : * @port: uart port
661 : * @rs485: rs485 settings
662 : *
663 : * Generic callback usable by 8250 uart drivers to activate rs485 settings
664 : * if the uart is incapable of driving RTS as a Transmit Enable signal in
665 : * hardware, relying on software emulation instead.
666 : */
667 0 : int serial8250_em485_config(struct uart_port *port, struct serial_rs485 *rs485)
668 : {
669 0 : struct uart_8250_port *up = up_to_u8250p(port);
670 :
671 : /* pick sane settings if the user hasn't */
672 0 : if (!!(rs485->flags & SER_RS485_RTS_ON_SEND) ==
673 0 : !!(rs485->flags & SER_RS485_RTS_AFTER_SEND)) {
674 0 : rs485->flags |= SER_RS485_RTS_ON_SEND;
675 0 : rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
676 : }
677 :
678 : /* clamp the delays to [0, 100ms] */
679 0 : rs485->delay_rts_before_send = min(rs485->delay_rts_before_send, 100U);
680 0 : rs485->delay_rts_after_send = min(rs485->delay_rts_after_send, 100U);
681 :
682 0 : memset(rs485->padding, 0, sizeof(rs485->padding));
683 0 : port->rs485 = *rs485;
684 :
685 0 : gpiod_set_value(port->rs485_term_gpio,
686 0 : rs485->flags & SER_RS485_TERMINATE_BUS);
687 :
688 : /*
689 : * Both serial8250_em485_init() and serial8250_em485_destroy()
690 : * are idempotent.
691 : */
692 0 : if (rs485->flags & SER_RS485_ENABLED) {
693 0 : int ret = serial8250_em485_init(up);
694 :
695 0 : if (ret) {
696 0 : rs485->flags &= ~SER_RS485_ENABLED;
697 0 : port->rs485.flags &= ~SER_RS485_ENABLED;
698 : }
699 0 : return ret;
700 : }
701 :
702 0 : serial8250_em485_destroy(up);
703 0 : return 0;
704 : }
705 : EXPORT_SYMBOL_GPL(serial8250_em485_config);
706 :
707 : /*
708 : * These two wrappers ensure that enable_runtime_pm_tx() can be called more than
709 : * once and disable_runtime_pm_tx() will still disable RPM because the fifo is
710 : * empty and the HW can idle again.
711 : */
712 397 : void serial8250_rpm_get_tx(struct uart_8250_port *p)
713 : {
714 397 : unsigned char rpm_active;
715 :
716 397 : if (!(p->capabilities & UART_CAP_RPM))
717 : return;
718 :
719 0 : rpm_active = xchg(&p->rpm_tx_active, 1);
720 0 : if (rpm_active)
721 : return;
722 0 : pm_runtime_get_sync(p->port.dev);
723 : }
724 : EXPORT_SYMBOL_GPL(serial8250_rpm_get_tx);
725 :
726 208 : void serial8250_rpm_put_tx(struct uart_8250_port *p)
727 : {
728 208 : unsigned char rpm_active;
729 :
730 208 : if (!(p->capabilities & UART_CAP_RPM))
731 : return;
732 :
733 0 : rpm_active = xchg(&p->rpm_tx_active, 0);
734 0 : if (!rpm_active)
735 : return;
736 0 : pm_runtime_mark_last_busy(p->port.dev);
737 0 : pm_runtime_put_autosuspend(p->port.dev);
738 : }
739 : EXPORT_SYMBOL_GPL(serial8250_rpm_put_tx);
740 :
741 : /*
742 : * IER sleep support. UARTs which have EFRs need the "extended
743 : * capability" bit enabled. Note that on XR16C850s, we need to
744 : * reset LCR to write to IER.
745 : */
746 1 : static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
747 : {
748 1 : unsigned char lcr = 0, efr = 0;
749 :
750 1 : serial8250_rpm_get(p);
751 :
752 1 : if (p->capabilities & UART_CAP_SLEEP) {
753 0 : if (p->capabilities & UART_CAP_EFR) {
754 0 : lcr = serial_in(p, UART_LCR);
755 0 : efr = serial_in(p, UART_EFR);
756 0 : serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
757 0 : serial_out(p, UART_EFR, UART_EFR_ECB);
758 0 : serial_out(p, UART_LCR, 0);
759 : }
760 0 : serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
761 0 : if (p->capabilities & UART_CAP_EFR) {
762 0 : serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
763 0 : serial_out(p, UART_EFR, efr);
764 0 : serial_out(p, UART_LCR, lcr);
765 : }
766 : }
767 :
768 1 : serial8250_rpm_put(p);
769 1 : }
770 :
771 : #ifdef CONFIG_SERIAL_8250_RSA
772 : /*
773 : * Attempts to turn on the RSA FIFO. Returns zero on failure.
774 : * We set the port uart clock rate if we succeed.
775 : */
776 : static int __enable_rsa(struct uart_8250_port *up)
777 : {
778 : unsigned char mode;
779 : int result;
780 :
781 : mode = serial_in(up, UART_RSA_MSR);
782 : result = mode & UART_RSA_MSR_FIFO;
783 :
784 : if (!result) {
785 : serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
786 : mode = serial_in(up, UART_RSA_MSR);
787 : result = mode & UART_RSA_MSR_FIFO;
788 : }
789 :
790 : if (result)
791 : up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
792 :
793 : return result;
794 : }
795 :
796 : static void enable_rsa(struct uart_8250_port *up)
797 : {
798 : if (up->port.type == PORT_RSA) {
799 : if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
800 : spin_lock_irq(&up->port.lock);
801 : __enable_rsa(up);
802 : spin_unlock_irq(&up->port.lock);
803 : }
804 : if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
805 : serial_out(up, UART_RSA_FRR, 0);
806 : }
807 : }
808 :
809 : /*
810 : * Attempts to turn off the RSA FIFO. Returns zero on failure.
811 : * It is unknown why interrupts were disabled in here. However,
812 : * the caller is expected to preserve this behaviour by grabbing
813 : * the spinlock before calling this function.
814 : */
815 : static void disable_rsa(struct uart_8250_port *up)
816 : {
817 : unsigned char mode;
818 : int result;
819 :
820 : if (up->port.type == PORT_RSA &&
821 : up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
822 : spin_lock_irq(&up->port.lock);
823 :
824 : mode = serial_in(up, UART_RSA_MSR);
825 : result = !(mode & UART_RSA_MSR_FIFO);
826 :
827 : if (!result) {
828 : serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
829 : mode = serial_in(up, UART_RSA_MSR);
830 : result = !(mode & UART_RSA_MSR_FIFO);
831 : }
832 :
833 : if (result)
834 : up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
835 : spin_unlock_irq(&up->port.lock);
836 : }
837 : }
838 : #endif /* CONFIG_SERIAL_8250_RSA */
839 :
840 : /*
841 : * This is a quickie test to see how big the FIFO is.
842 : * It doesn't work at all the time, more's the pity.
843 : */
844 : static int size_fifo(struct uart_8250_port *up)
845 : {
846 : unsigned char old_fcr, old_mcr, old_lcr;
847 : unsigned short old_dl;
848 : int count;
849 :
850 : old_lcr = serial_in(up, UART_LCR);
851 : serial_out(up, UART_LCR, 0);
852 : old_fcr = serial_in(up, UART_FCR);
853 : old_mcr = serial8250_in_MCR(up);
854 : serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
855 : UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
856 : serial8250_out_MCR(up, UART_MCR_LOOP);
857 : serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
858 : old_dl = serial_dl_read(up);
859 : serial_dl_write(up, 0x0001);
860 : serial_out(up, UART_LCR, 0x03);
861 : for (count = 0; count < 256; count++)
862 : serial_out(up, UART_TX, count);
863 : mdelay(20);/* FIXME - schedule_timeout */
864 : for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
865 : (count < 256); count++)
866 : serial_in(up, UART_RX);
867 : serial_out(up, UART_FCR, old_fcr);
868 : serial8250_out_MCR(up, old_mcr);
869 : serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
870 : serial_dl_write(up, old_dl);
871 : serial_out(up, UART_LCR, old_lcr);
872 :
873 : return count;
874 : }
875 :
876 : /*
877 : * Read UART ID using the divisor method - set DLL and DLM to zero
878 : * and the revision will be in DLL and device type in DLM. We
879 : * preserve the device state across this.
880 : */
881 : static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
882 : {
883 : unsigned char old_lcr;
884 : unsigned int id, old_dl;
885 :
886 : old_lcr = serial_in(p, UART_LCR);
887 : serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
888 : old_dl = serial_dl_read(p);
889 : serial_dl_write(p, 0);
890 : id = serial_dl_read(p);
891 : serial_dl_write(p, old_dl);
892 :
893 : serial_out(p, UART_LCR, old_lcr);
894 :
895 : return id;
896 : }
897 :
898 : /*
899 : * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
900 : * When this function is called we know it is at least a StarTech
901 : * 16650 V2, but it might be one of several StarTech UARTs, or one of
902 : * its clones. (We treat the broken original StarTech 16650 V1 as a
903 : * 16550, and why not? Startech doesn't seem to even acknowledge its
904 : * existence.)
905 : *
906 : * What evil have men's minds wrought...
907 : */
908 : static void autoconfig_has_efr(struct uart_8250_port *up)
909 : {
910 : unsigned int id1, id2, id3, rev;
911 :
912 : /*
913 : * Everything with an EFR has SLEEP
914 : */
915 : up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
916 :
917 : /*
918 : * First we check to see if it's an Oxford Semiconductor UART.
919 : *
920 : * If we have to do this here because some non-National
921 : * Semiconductor clone chips lock up if you try writing to the
922 : * LSR register (which serial_icr_read does)
923 : */
924 :
925 : /*
926 : * Check for Oxford Semiconductor 16C950.
927 : *
928 : * EFR [4] must be set else this test fails.
929 : *
930 : * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
931 : * claims that it's needed for 952 dual UART's (which are not
932 : * recommended for new designs).
933 : */
934 : up->acr = 0;
935 : serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
936 : serial_out(up, UART_EFR, UART_EFR_ECB);
937 : serial_out(up, UART_LCR, 0x00);
938 : id1 = serial_icr_read(up, UART_ID1);
939 : id2 = serial_icr_read(up, UART_ID2);
940 : id3 = serial_icr_read(up, UART_ID3);
941 : rev = serial_icr_read(up, UART_REV);
942 :
943 : DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
944 :
945 : if (id1 == 0x16 && id2 == 0xC9 &&
946 : (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
947 : up->port.type = PORT_16C950;
948 :
949 : /*
950 : * Enable work around for the Oxford Semiconductor 952 rev B
951 : * chip which causes it to seriously miscalculate baud rates
952 : * when DLL is 0.
953 : */
954 : if (id3 == 0x52 && rev == 0x01)
955 : up->bugs |= UART_BUG_QUOT;
956 : return;
957 : }
958 :
959 : /*
960 : * We check for a XR16C850 by setting DLL and DLM to 0, and then
961 : * reading back DLL and DLM. The chip type depends on the DLM
962 : * value read back:
963 : * 0x10 - XR16C850 and the DLL contains the chip revision.
964 : * 0x12 - XR16C2850.
965 : * 0x14 - XR16C854.
966 : */
967 : id1 = autoconfig_read_divisor_id(up);
968 : DEBUG_AUTOCONF("850id=%04x ", id1);
969 :
970 : id2 = id1 >> 8;
971 : if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
972 : up->port.type = PORT_16850;
973 : return;
974 : }
975 :
976 : /*
977 : * It wasn't an XR16C850.
978 : *
979 : * We distinguish between the '654 and the '650 by counting
980 : * how many bytes are in the FIFO. I'm using this for now,
981 : * since that's the technique that was sent to me in the
982 : * serial driver update, but I'm not convinced this works.
983 : * I've had problems doing this in the past. -TYT
984 : */
985 : if (size_fifo(up) == 64)
986 : up->port.type = PORT_16654;
987 : else
988 : up->port.type = PORT_16650V2;
989 : }
990 :
991 : /*
992 : * We detected a chip without a FIFO. Only two fall into
993 : * this category - the original 8250 and the 16450. The
994 : * 16450 has a scratch register (accessible with LCR=0)
995 : */
996 0 : static void autoconfig_8250(struct uart_8250_port *up)
997 : {
998 0 : unsigned char scratch, status1, status2;
999 :
1000 0 : up->port.type = PORT_8250;
1001 :
1002 0 : scratch = serial_in(up, UART_SCR);
1003 0 : serial_out(up, UART_SCR, 0xa5);
1004 0 : status1 = serial_in(up, UART_SCR);
1005 0 : serial_out(up, UART_SCR, 0x5a);
1006 0 : status2 = serial_in(up, UART_SCR);
1007 0 : serial_out(up, UART_SCR, scratch);
1008 :
1009 0 : if (status1 == 0xa5 && status2 == 0x5a)
1010 0 : up->port.type = PORT_16450;
1011 0 : }
1012 :
1013 : static int broken_efr(struct uart_8250_port *up)
1014 : {
1015 : /*
1016 : * Exar ST16C2550 "A2" devices incorrectly detect as
1017 : * having an EFR, and report an ID of 0x0201. See
1018 : * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
1019 : */
1020 : if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
1021 : return 1;
1022 :
1023 : return 0;
1024 : }
1025 :
1026 : /*
1027 : * We know that the chip has FIFOs. Does it have an EFR? The
1028 : * EFR is located in the same register position as the IIR and
1029 : * we know the top two bits of the IIR are currently set. The
1030 : * EFR should contain zero. Try to read the EFR.
1031 : */
1032 1 : static void autoconfig_16550a(struct uart_8250_port *up)
1033 : {
1034 1 : unsigned char status1, status2;
1035 1 : unsigned int iersave;
1036 :
1037 1 : up->port.type = PORT_16550A;
1038 1 : up->capabilities |= UART_CAP_FIFO;
1039 :
1040 1 : if (!IS_ENABLED(CONFIG_SERIAL_8250_16550A_VARIANTS))
1041 1 : return;
1042 :
1043 : /*
1044 : * Check for presence of the EFR when DLAB is set.
1045 : * Only ST16C650V1 UARTs pass this test.
1046 : */
1047 : serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1048 : if (serial_in(up, UART_EFR) == 0) {
1049 : serial_out(up, UART_EFR, 0xA8);
1050 : if (serial_in(up, UART_EFR) != 0) {
1051 : DEBUG_AUTOCONF("EFRv1 ");
1052 : up->port.type = PORT_16650;
1053 : up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
1054 : } else {
1055 : serial_out(up, UART_LCR, 0);
1056 : serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
1057 : UART_FCR7_64BYTE);
1058 : status1 = serial_in(up, UART_IIR) >> 5;
1059 : serial_out(up, UART_FCR, 0);
1060 : serial_out(up, UART_LCR, 0);
1061 :
1062 : if (status1 == 7)
1063 : up->port.type = PORT_16550A_FSL64;
1064 : else
1065 : DEBUG_AUTOCONF("Motorola 8xxx DUART ");
1066 : }
1067 : serial_out(up, UART_EFR, 0);
1068 : return;
1069 : }
1070 :
1071 : /*
1072 : * Maybe it requires 0xbf to be written to the LCR.
1073 : * (other ST16C650V2 UARTs, TI16C752A, etc)
1074 : */
1075 : serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1076 : if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
1077 : DEBUG_AUTOCONF("EFRv2 ");
1078 : autoconfig_has_efr(up);
1079 : return;
1080 : }
1081 :
1082 : /*
1083 : * Check for a National Semiconductor SuperIO chip.
1084 : * Attempt to switch to bank 2, read the value of the LOOP bit
1085 : * from EXCR1. Switch back to bank 0, change it in MCR. Then
1086 : * switch back to bank 2, read it from EXCR1 again and check
1087 : * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1088 : */
1089 : serial_out(up, UART_LCR, 0);
1090 : status1 = serial8250_in_MCR(up);
1091 : serial_out(up, UART_LCR, 0xE0);
1092 : status2 = serial_in(up, 0x02); /* EXCR1 */
1093 :
1094 : if (!((status2 ^ status1) & UART_MCR_LOOP)) {
1095 : serial_out(up, UART_LCR, 0);
1096 : serial8250_out_MCR(up, status1 ^ UART_MCR_LOOP);
1097 : serial_out(up, UART_LCR, 0xE0);
1098 : status2 = serial_in(up, 0x02); /* EXCR1 */
1099 : serial_out(up, UART_LCR, 0);
1100 : serial8250_out_MCR(up, status1);
1101 :
1102 : if ((status2 ^ status1) & UART_MCR_LOOP) {
1103 : unsigned short quot;
1104 :
1105 : serial_out(up, UART_LCR, 0xE0);
1106 :
1107 : quot = serial_dl_read(up);
1108 : quot <<= 3;
1109 :
1110 : if (ns16550a_goto_highspeed(up))
1111 : serial_dl_write(up, quot);
1112 :
1113 : serial_out(up, UART_LCR, 0);
1114 :
1115 : up->port.uartclk = 921600*16;
1116 : up->port.type = PORT_NS16550A;
1117 : up->capabilities |= UART_NATSEMI;
1118 : return;
1119 : }
1120 : }
1121 :
1122 : /*
1123 : * No EFR. Try to detect a TI16750, which only sets bit 5 of
1124 : * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1125 : * Try setting it with and without DLAB set. Cheap clones
1126 : * set bit 5 without DLAB set.
1127 : */
1128 : serial_out(up, UART_LCR, 0);
1129 : serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1130 : status1 = serial_in(up, UART_IIR) >> 5;
1131 : serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1132 : serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1133 : serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1134 : status2 = serial_in(up, UART_IIR) >> 5;
1135 : serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1136 : serial_out(up, UART_LCR, 0);
1137 :
1138 : DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1139 :
1140 : if (status1 == 6 && status2 == 7) {
1141 : up->port.type = PORT_16750;
1142 : up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1143 : return;
1144 : }
1145 :
1146 : /*
1147 : * Try writing and reading the UART_IER_UUE bit (b6).
1148 : * If it works, this is probably one of the Xscale platform's
1149 : * internal UARTs.
1150 : * We're going to explicitly set the UUE bit to 0 before
1151 : * trying to write and read a 1 just to make sure it's not
1152 : * already a 1 and maybe locked there before we even start start.
1153 : */
1154 : iersave = serial_in(up, UART_IER);
1155 : serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1156 : if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1157 : /*
1158 : * OK it's in a known zero state, try writing and reading
1159 : * without disturbing the current state of the other bits.
1160 : */
1161 : serial_out(up, UART_IER, iersave | UART_IER_UUE);
1162 : if (serial_in(up, UART_IER) & UART_IER_UUE) {
1163 : /*
1164 : * It's an Xscale.
1165 : * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1166 : */
1167 : DEBUG_AUTOCONF("Xscale ");
1168 : up->port.type = PORT_XSCALE;
1169 : up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1170 : return;
1171 : }
1172 : } else {
1173 : /*
1174 : * If we got here we couldn't force the IER_UUE bit to 0.
1175 : * Log it and continue.
1176 : */
1177 : DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1178 : }
1179 : serial_out(up, UART_IER, iersave);
1180 :
1181 : /*
1182 : * We distinguish between 16550A and U6 16550A by counting
1183 : * how many bytes are in the FIFO.
1184 : */
1185 : if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1186 : up->port.type = PORT_U6_16550A;
1187 : up->capabilities |= UART_CAP_AFE;
1188 : }
1189 : }
1190 :
1191 : /*
1192 : * This routine is called by rs_init() to initialize a specific serial
1193 : * port. It determines what type of UART chip this serial port is
1194 : * using: 8250, 16450, 16550, 16550A. The important question is
1195 : * whether or not this UART is a 16550A or not, since this will
1196 : * determine whether or not we can use its FIFO features or not.
1197 : */
1198 4 : static void autoconfig(struct uart_8250_port *up)
1199 : {
1200 4 : unsigned char status1, scratch, scratch2, scratch3;
1201 4 : unsigned char save_lcr, save_mcr;
1202 4 : struct uart_port *port = &up->port;
1203 4 : unsigned long flags;
1204 4 : unsigned int old_capabilities;
1205 :
1206 4 : if (!port->iobase && !port->mapbase && !port->membase)
1207 : return;
1208 :
1209 4 : DEBUG_AUTOCONF("%s: autoconf (0x%04lx, 0x%p): ",
1210 : port->name, port->iobase, port->membase);
1211 :
1212 : /*
1213 : * We really do need global IRQs disabled here - we're going to
1214 : * be frobbing the chips IRQ enable register to see if it exists.
1215 : */
1216 4 : spin_lock_irqsave(&port->lock, flags);
1217 :
1218 4 : up->capabilities = 0;
1219 4 : up->bugs = 0;
1220 :
1221 4 : if (!(port->flags & UPF_BUGGY_UART)) {
1222 : /*
1223 : * Do a simple existence test first; if we fail this,
1224 : * there's no point trying anything else.
1225 : *
1226 : * 0x80 is used as a nonsense port to prevent against
1227 : * false positives due to ISA bus float. The
1228 : * assumption is that 0x80 is a non-existent port;
1229 : * which should be safe since include/asm/io.h also
1230 : * makes this assumption.
1231 : *
1232 : * Note: this is safe as long as MCR bit 4 is clear
1233 : * and the device is in "PC" mode.
1234 : */
1235 4 : scratch = serial_in(up, UART_IER);
1236 4 : serial_out(up, UART_IER, 0);
1237 : #ifdef __i386__
1238 : outb(0xff, 0x080);
1239 : #endif
1240 : /*
1241 : * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1242 : * 16C754B) allow only to modify them if an EFR bit is set.
1243 : */
1244 4 : scratch2 = serial_in(up, UART_IER) & 0x0f;
1245 4 : serial_out(up, UART_IER, 0x0F);
1246 : #ifdef __i386__
1247 : outb(0, 0x080);
1248 : #endif
1249 4 : scratch3 = serial_in(up, UART_IER) & 0x0f;
1250 4 : serial_out(up, UART_IER, scratch);
1251 4 : if (scratch2 != 0 || scratch3 != 0x0F) {
1252 : /*
1253 : * We failed; there's nothing here
1254 : */
1255 3 : spin_unlock_irqrestore(&port->lock, flags);
1256 3 : DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1257 : scratch2, scratch3);
1258 3 : goto out;
1259 : }
1260 : }
1261 :
1262 1 : save_mcr = serial8250_in_MCR(up);
1263 1 : save_lcr = serial_in(up, UART_LCR);
1264 :
1265 : /*
1266 : * Check to see if a UART is really there. Certain broken
1267 : * internal modems based on the Rockwell chipset fail this
1268 : * test, because they apparently don't implement the loopback
1269 : * test mode. So this test is skipped on the COM 1 through
1270 : * COM 4 ports. This *should* be safe, since no board
1271 : * manufacturer would be stupid enough to design a board
1272 : * that conflicts with COM 1-4 --- we hope!
1273 : */
1274 1 : if (!(port->flags & UPF_SKIP_TEST)) {
1275 0 : serial8250_out_MCR(up, UART_MCR_LOOP | 0x0A);
1276 0 : status1 = serial_in(up, UART_MSR) & 0xF0;
1277 0 : serial8250_out_MCR(up, save_mcr);
1278 0 : if (status1 != 0x90) {
1279 0 : spin_unlock_irqrestore(&port->lock, flags);
1280 0 : DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1281 : status1);
1282 0 : goto out;
1283 : }
1284 : }
1285 :
1286 : /*
1287 : * We're pretty sure there's a port here. Lets find out what
1288 : * type of port it is. The IIR top two bits allows us to find
1289 : * out if it's 8250 or 16450, 16550, 16550A or later. This
1290 : * determines what we test for next.
1291 : *
1292 : * We also initialise the EFR (if any) to zero for later. The
1293 : * EFR occupies the same register location as the FCR and IIR.
1294 : */
1295 1 : serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1296 1 : serial_out(up, UART_EFR, 0);
1297 1 : serial_out(up, UART_LCR, 0);
1298 :
1299 1 : serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1300 1 : scratch = serial_in(up, UART_IIR) >> 6;
1301 :
1302 1 : switch (scratch) {
1303 0 : case 0:
1304 0 : autoconfig_8250(up);
1305 0 : break;
1306 0 : case 1:
1307 0 : port->type = PORT_UNKNOWN;
1308 0 : break;
1309 0 : case 2:
1310 0 : port->type = PORT_16550;
1311 0 : break;
1312 : case 3:
1313 1 : autoconfig_16550a(up);
1314 : break;
1315 : }
1316 :
1317 : #ifdef CONFIG_SERIAL_8250_RSA
1318 : /*
1319 : * Only probe for RSA ports if we got the region.
1320 : */
1321 : if (port->type == PORT_16550A && up->probe & UART_PROBE_RSA &&
1322 : __enable_rsa(up))
1323 : port->type = PORT_RSA;
1324 : #endif
1325 :
1326 1 : serial_out(up, UART_LCR, save_lcr);
1327 :
1328 1 : port->fifosize = uart_config[up->port.type].fifo_size;
1329 1 : old_capabilities = up->capabilities;
1330 1 : up->capabilities = uart_config[port->type].flags;
1331 1 : up->tx_loadsz = uart_config[port->type].tx_loadsz;
1332 :
1333 1 : if (port->type == PORT_UNKNOWN)
1334 0 : goto out_lock;
1335 :
1336 : /*
1337 : * Reset the UART.
1338 : */
1339 : #ifdef CONFIG_SERIAL_8250_RSA
1340 : if (port->type == PORT_RSA)
1341 : serial_out(up, UART_RSA_FRR, 0);
1342 : #endif
1343 1 : serial8250_out_MCR(up, save_mcr);
1344 1 : serial8250_clear_fifos(up);
1345 1 : serial_in(up, UART_RX);
1346 1 : if (up->capabilities & UART_CAP_UUE)
1347 0 : serial_out(up, UART_IER, UART_IER_UUE);
1348 : else
1349 1 : serial_out(up, UART_IER, 0);
1350 :
1351 1 : out_lock:
1352 1 : spin_unlock_irqrestore(&port->lock, flags);
1353 :
1354 : /*
1355 : * Check if the device is a Fintek F81216A
1356 : */
1357 1 : if (port->type == PORT_16550A && port->iotype == UPIO_PORT)
1358 1 : fintek_8250_probe(up);
1359 :
1360 1 : if (up->capabilities != old_capabilities) {
1361 0 : dev_warn(port->dev, "detected caps %08x should be %08x\n",
1362 : old_capabilities, up->capabilities);
1363 : }
1364 1 : out:
1365 4 : DEBUG_AUTOCONF("iir=%d ", scratch);
1366 4 : DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1367 : }
1368 :
1369 0 : static void autoconfig_irq(struct uart_8250_port *up)
1370 : {
1371 0 : struct uart_port *port = &up->port;
1372 0 : unsigned char save_mcr, save_ier;
1373 0 : unsigned char save_ICP = 0;
1374 0 : unsigned int ICP = 0;
1375 0 : unsigned long irqs;
1376 0 : int irq;
1377 :
1378 0 : if (port->flags & UPF_FOURPORT) {
1379 0 : ICP = (port->iobase & 0xfe0) | 0x1f;
1380 0 : save_ICP = inb_p(ICP);
1381 0 : outb_p(0x80, ICP);
1382 0 : inb_p(ICP);
1383 : }
1384 :
1385 0 : if (uart_console(port))
1386 0 : console_lock();
1387 :
1388 : /* forget possible initially masked and pending IRQ */
1389 0 : probe_irq_off(probe_irq_on());
1390 0 : save_mcr = serial8250_in_MCR(up);
1391 0 : save_ier = serial_in(up, UART_IER);
1392 0 : serial8250_out_MCR(up, UART_MCR_OUT1 | UART_MCR_OUT2);
1393 :
1394 0 : irqs = probe_irq_on();
1395 0 : serial8250_out_MCR(up, 0);
1396 0 : udelay(10);
1397 0 : if (port->flags & UPF_FOURPORT) {
1398 0 : serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
1399 : } else {
1400 0 : serial8250_out_MCR(up,
1401 : UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1402 : }
1403 0 : serial_out(up, UART_IER, 0x0f); /* enable all intrs */
1404 0 : serial_in(up, UART_LSR);
1405 0 : serial_in(up, UART_RX);
1406 0 : serial_in(up, UART_IIR);
1407 0 : serial_in(up, UART_MSR);
1408 0 : serial_out(up, UART_TX, 0xFF);
1409 0 : udelay(20);
1410 0 : irq = probe_irq_off(irqs);
1411 :
1412 0 : serial8250_out_MCR(up, save_mcr);
1413 0 : serial_out(up, UART_IER, save_ier);
1414 :
1415 0 : if (port->flags & UPF_FOURPORT)
1416 0 : outb_p(save_ICP, ICP);
1417 :
1418 0 : if (uart_console(port))
1419 0 : console_unlock();
1420 :
1421 0 : port->irq = (irq > 0) ? irq : 0;
1422 0 : }
1423 :
1424 0 : static void serial8250_stop_rx(struct uart_port *port)
1425 : {
1426 0 : struct uart_8250_port *up = up_to_u8250p(port);
1427 :
1428 0 : serial8250_rpm_get(up);
1429 :
1430 0 : up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1431 0 : up->port.read_status_mask &= ~UART_LSR_DR;
1432 0 : serial_port_out(port, UART_IER, up->ier);
1433 :
1434 0 : serial8250_rpm_put(up);
1435 0 : }
1436 :
1437 : /**
1438 : * serial8250_em485_stop_tx() - generic ->rs485_stop_tx() callback
1439 : * @p: uart 8250 port
1440 : *
1441 : * Generic callback usable by 8250 uart drivers to stop rs485 transmission.
1442 : */
1443 0 : void serial8250_em485_stop_tx(struct uart_8250_port *p)
1444 : {
1445 0 : unsigned char mcr = serial8250_in_MCR(p);
1446 :
1447 0 : if (p->port.rs485.flags & SER_RS485_RTS_AFTER_SEND)
1448 0 : mcr |= UART_MCR_RTS;
1449 : else
1450 0 : mcr &= ~UART_MCR_RTS;
1451 0 : serial8250_out_MCR(p, mcr);
1452 :
1453 : /*
1454 : * Empty the RX FIFO, we are not interested in anything
1455 : * received during the half-duplex transmission.
1456 : * Enable previously disabled RX interrupts.
1457 : */
1458 0 : if (!(p->port.rs485.flags & SER_RS485_RX_DURING_TX)) {
1459 0 : serial8250_clear_and_reinit_fifos(p);
1460 :
1461 0 : p->ier |= UART_IER_RLSI | UART_IER_RDI;
1462 0 : serial_port_out(&p->port, UART_IER, p->ier);
1463 : }
1464 0 : }
1465 : EXPORT_SYMBOL_GPL(serial8250_em485_stop_tx);
1466 :
1467 0 : static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t)
1468 : {
1469 0 : struct uart_8250_em485 *em485;
1470 0 : struct uart_8250_port *p;
1471 0 : unsigned long flags;
1472 :
1473 0 : em485 = container_of(t, struct uart_8250_em485, stop_tx_timer);
1474 0 : p = em485->port;
1475 :
1476 0 : serial8250_rpm_get(p);
1477 0 : spin_lock_irqsave(&p->port.lock, flags);
1478 0 : if (em485->active_timer == &em485->stop_tx_timer) {
1479 0 : p->rs485_stop_tx(p);
1480 0 : em485->active_timer = NULL;
1481 0 : em485->tx_stopped = true;
1482 : }
1483 0 : spin_unlock_irqrestore(&p->port.lock, flags);
1484 0 : serial8250_rpm_put(p);
1485 0 : return HRTIMER_NORESTART;
1486 : }
1487 :
1488 0 : static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
1489 : {
1490 0 : long sec = msec / 1000;
1491 0 : long nsec = (msec % 1000) * 1000000;
1492 0 : ktime_t t = ktime_set(sec, nsec);
1493 :
1494 0 : hrtimer_start(hrt, t, HRTIMER_MODE_REL);
1495 0 : }
1496 :
1497 0 : static void __stop_tx_rs485(struct uart_8250_port *p)
1498 : {
1499 0 : struct uart_8250_em485 *em485 = p->em485;
1500 :
1501 : /*
1502 : * rs485_stop_tx() is going to set RTS according to config
1503 : * AND flush RX FIFO if required.
1504 : */
1505 0 : if (p->port.rs485.delay_rts_after_send > 0) {
1506 0 : em485->active_timer = &em485->stop_tx_timer;
1507 0 : start_hrtimer_ms(&em485->stop_tx_timer,
1508 0 : p->port.rs485.delay_rts_after_send);
1509 : } else {
1510 0 : p->rs485_stop_tx(p);
1511 0 : em485->active_timer = NULL;
1512 0 : em485->tx_stopped = true;
1513 : }
1514 0 : }
1515 :
1516 208 : static inline void __do_stop_tx(struct uart_8250_port *p)
1517 : {
1518 208 : if (serial8250_clear_THRI(p))
1519 208 : serial8250_rpm_put_tx(p);
1520 208 : }
1521 :
1522 208 : static inline void __stop_tx(struct uart_8250_port *p)
1523 : {
1524 208 : struct uart_8250_em485 *em485 = p->em485;
1525 :
1526 208 : if (em485) {
1527 0 : unsigned char lsr = serial_in(p, UART_LSR);
1528 : /*
1529 : * To provide required timeing and allow FIFO transfer,
1530 : * __stop_tx_rs485() must be called only when both FIFO and
1531 : * shift register are empty. It is for device driver to enable
1532 : * interrupt on TEMT.
1533 : */
1534 0 : if ((lsr & BOTH_EMPTY) != BOTH_EMPTY)
1535 : return;
1536 :
1537 0 : __stop_tx_rs485(p);
1538 : }
1539 208 : __do_stop_tx(p);
1540 : }
1541 :
1542 0 : static void serial8250_stop_tx(struct uart_port *port)
1543 : {
1544 0 : struct uart_8250_port *up = up_to_u8250p(port);
1545 :
1546 0 : serial8250_rpm_get(up);
1547 0 : __stop_tx(up);
1548 :
1549 : /*
1550 : * We really want to stop the transmitter from sending.
1551 : */
1552 0 : if (port->type == PORT_16C950) {
1553 0 : up->acr |= UART_ACR_TXDIS;
1554 0 : serial_icr_write(up, UART_ACR, up->acr);
1555 : }
1556 0 : serial8250_rpm_put(up);
1557 0 : }
1558 :
1559 397 : static inline void __start_tx(struct uart_port *port)
1560 : {
1561 397 : struct uart_8250_port *up = up_to_u8250p(port);
1562 :
1563 397 : if (up->dma && !up->dma->tx_dma(up))
1564 : return;
1565 :
1566 397 : if (serial8250_set_THRI(up)) {
1567 208 : if (up->bugs & UART_BUG_TXEN) {
1568 0 : unsigned char lsr;
1569 :
1570 0 : lsr = serial_in(up, UART_LSR);
1571 0 : up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1572 0 : if (lsr & UART_LSR_THRE)
1573 0 : serial8250_tx_chars(up);
1574 : }
1575 : }
1576 :
1577 : /*
1578 : * Re-enable the transmitter if we disabled it.
1579 : */
1580 397 : if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1581 0 : up->acr &= ~UART_ACR_TXDIS;
1582 0 : serial_icr_write(up, UART_ACR, up->acr);
1583 : }
1584 : }
1585 :
1586 : /**
1587 : * serial8250_em485_start_tx() - generic ->rs485_start_tx() callback
1588 : * @up: uart 8250 port
1589 : *
1590 : * Generic callback usable by 8250 uart drivers to start rs485 transmission.
1591 : * Assumes that setting the RTS bit in the MCR register means RTS is high.
1592 : * (Some chips use inverse semantics.) Further assumes that reception is
1593 : * stoppable by disabling the UART_IER_RDI interrupt. (Some chips set the
1594 : * UART_LSR_DR bit even when UART_IER_RDI is disabled, foiling this approach.)
1595 : */
1596 0 : void serial8250_em485_start_tx(struct uart_8250_port *up)
1597 : {
1598 0 : unsigned char mcr = serial8250_in_MCR(up);
1599 :
1600 0 : if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX))
1601 0 : serial8250_stop_rx(&up->port);
1602 :
1603 0 : if (up->port.rs485.flags & SER_RS485_RTS_ON_SEND)
1604 0 : mcr |= UART_MCR_RTS;
1605 : else
1606 0 : mcr &= ~UART_MCR_RTS;
1607 0 : serial8250_out_MCR(up, mcr);
1608 0 : }
1609 : EXPORT_SYMBOL_GPL(serial8250_em485_start_tx);
1610 :
1611 0 : static inline void start_tx_rs485(struct uart_port *port)
1612 : {
1613 0 : struct uart_8250_port *up = up_to_u8250p(port);
1614 0 : struct uart_8250_em485 *em485 = up->em485;
1615 :
1616 0 : em485->active_timer = NULL;
1617 :
1618 0 : if (em485->tx_stopped) {
1619 0 : em485->tx_stopped = false;
1620 :
1621 0 : up->rs485_start_tx(up);
1622 :
1623 0 : if (up->port.rs485.delay_rts_before_send > 0) {
1624 0 : em485->active_timer = &em485->start_tx_timer;
1625 0 : start_hrtimer_ms(&em485->start_tx_timer,
1626 0 : up->port.rs485.delay_rts_before_send);
1627 0 : return;
1628 : }
1629 : }
1630 :
1631 0 : __start_tx(port);
1632 : }
1633 :
1634 0 : static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t)
1635 : {
1636 0 : struct uart_8250_em485 *em485;
1637 0 : struct uart_8250_port *p;
1638 0 : unsigned long flags;
1639 :
1640 0 : em485 = container_of(t, struct uart_8250_em485, start_tx_timer);
1641 0 : p = em485->port;
1642 :
1643 0 : spin_lock_irqsave(&p->port.lock, flags);
1644 0 : if (em485->active_timer == &em485->start_tx_timer) {
1645 0 : __start_tx(&p->port);
1646 0 : em485->active_timer = NULL;
1647 : }
1648 0 : spin_unlock_irqrestore(&p->port.lock, flags);
1649 0 : return HRTIMER_NORESTART;
1650 : }
1651 :
1652 397 : static void serial8250_start_tx(struct uart_port *port)
1653 : {
1654 397 : struct uart_8250_port *up = up_to_u8250p(port);
1655 397 : struct uart_8250_em485 *em485 = up->em485;
1656 :
1657 397 : serial8250_rpm_get_tx(up);
1658 :
1659 397 : if (em485 &&
1660 0 : em485->active_timer == &em485->start_tx_timer)
1661 : return;
1662 :
1663 397 : if (em485)
1664 0 : start_tx_rs485(port);
1665 : else
1666 397 : __start_tx(port);
1667 : }
1668 :
1669 0 : static void serial8250_throttle(struct uart_port *port)
1670 : {
1671 0 : port->throttle(port);
1672 0 : }
1673 :
1674 0 : static void serial8250_unthrottle(struct uart_port *port)
1675 : {
1676 0 : port->unthrottle(port);
1677 0 : }
1678 :
1679 0 : static void serial8250_disable_ms(struct uart_port *port)
1680 : {
1681 0 : struct uart_8250_port *up = up_to_u8250p(port);
1682 :
1683 : /* no MSR capabilities */
1684 0 : if (up->bugs & UART_BUG_NOMSR)
1685 : return;
1686 :
1687 0 : mctrl_gpio_disable_ms(up->gpios);
1688 :
1689 0 : up->ier &= ~UART_IER_MSI;
1690 0 : serial_port_out(port, UART_IER, up->ier);
1691 : }
1692 :
1693 0 : static void serial8250_enable_ms(struct uart_port *port)
1694 : {
1695 0 : struct uart_8250_port *up = up_to_u8250p(port);
1696 :
1697 : /* no MSR capabilities */
1698 0 : if (up->bugs & UART_BUG_NOMSR)
1699 : return;
1700 :
1701 0 : mctrl_gpio_enable_ms(up->gpios);
1702 :
1703 0 : up->ier |= UART_IER_MSI;
1704 :
1705 0 : serial8250_rpm_get(up);
1706 0 : serial_port_out(port, UART_IER, up->ier);
1707 0 : serial8250_rpm_put(up);
1708 : }
1709 :
1710 0 : void serial8250_read_char(struct uart_8250_port *up, unsigned char lsr)
1711 : {
1712 0 : struct uart_port *port = &up->port;
1713 0 : unsigned char ch;
1714 0 : char flag = TTY_NORMAL;
1715 :
1716 0 : if (likely(lsr & UART_LSR_DR))
1717 0 : ch = serial_in(up, UART_RX);
1718 : else
1719 : /*
1720 : * Intel 82571 has a Serial Over Lan device that will
1721 : * set UART_LSR_BI without setting UART_LSR_DR when
1722 : * it receives a break. To avoid reading from the
1723 : * receive buffer without UART_LSR_DR bit set, we
1724 : * just force the read character to be 0
1725 : */
1726 : ch = 0;
1727 :
1728 0 : port->icount.rx++;
1729 :
1730 0 : lsr |= up->lsr_saved_flags;
1731 0 : up->lsr_saved_flags = 0;
1732 :
1733 0 : if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1734 0 : if (lsr & UART_LSR_BI) {
1735 0 : lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1736 0 : port->icount.brk++;
1737 : /*
1738 : * We do the SysRQ and SAK checking
1739 : * here because otherwise the break
1740 : * may get masked by ignore_status_mask
1741 : * or read_status_mask.
1742 : */
1743 0 : if (uart_handle_break(port))
1744 : return;
1745 0 : } else if (lsr & UART_LSR_PE)
1746 0 : port->icount.parity++;
1747 0 : else if (lsr & UART_LSR_FE)
1748 0 : port->icount.frame++;
1749 0 : if (lsr & UART_LSR_OE)
1750 0 : port->icount.overrun++;
1751 :
1752 : /*
1753 : * Mask off conditions which should be ignored.
1754 : */
1755 0 : lsr &= port->read_status_mask;
1756 :
1757 0 : if (lsr & UART_LSR_BI) {
1758 : dev_dbg(port->dev, "handling break\n");
1759 : flag = TTY_BREAK;
1760 0 : } else if (lsr & UART_LSR_PE)
1761 : flag = TTY_PARITY;
1762 0 : else if (lsr & UART_LSR_FE)
1763 0 : flag = TTY_FRAME;
1764 : }
1765 0 : if (uart_prepare_sysrq_char(port, ch))
1766 : return;
1767 :
1768 0 : uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1769 : }
1770 : EXPORT_SYMBOL_GPL(serial8250_read_char);
1771 :
1772 : /*
1773 : * serial8250_rx_chars: processes according to the passed in LSR
1774 : * value, and returns the remaining LSR bits not handled
1775 : * by this Rx routine.
1776 : */
1777 0 : unsigned char serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1778 : {
1779 0 : struct uart_port *port = &up->port;
1780 0 : int max_count = 256;
1781 :
1782 0 : do {
1783 0 : serial8250_read_char(up, lsr);
1784 0 : if (--max_count == 0)
1785 : break;
1786 0 : lsr = serial_in(up, UART_LSR);
1787 0 : } while (lsr & (UART_LSR_DR | UART_LSR_BI));
1788 :
1789 0 : tty_flip_buffer_push(&port->state->port);
1790 0 : return lsr;
1791 : }
1792 : EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1793 :
1794 750 : void serial8250_tx_chars(struct uart_8250_port *up)
1795 : {
1796 750 : struct uart_port *port = &up->port;
1797 750 : struct circ_buf *xmit = &port->state->xmit;
1798 750 : int count;
1799 :
1800 750 : if (port->x_char) {
1801 0 : serial_out(up, UART_TX, port->x_char);
1802 0 : port->icount.tx++;
1803 0 : port->x_char = 0;
1804 0 : return;
1805 : }
1806 750 : if (uart_tx_stopped(port)) {
1807 0 : serial8250_stop_tx(port);
1808 0 : return;
1809 : }
1810 750 : if (uart_circ_empty(xmit)) {
1811 38 : __stop_tx(up);
1812 38 : return;
1813 : }
1814 :
1815 712 : count = up->tx_loadsz;
1816 9826 : do {
1817 9826 : serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1818 9826 : xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1819 9826 : port->icount.tx++;
1820 9826 : if (uart_circ_empty(xmit))
1821 : break;
1822 9656 : if ((up->capabilities & UART_CAP_HFIFO) &&
1823 0 : (serial_in(up, UART_LSR) & BOTH_EMPTY) != BOTH_EMPTY)
1824 : break;
1825 : /* The BCM2835 MINI UART THRE bit is really a not-full bit. */
1826 9656 : if ((up->capabilities & UART_CAP_MINI) &&
1827 0 : !(serial_in(up, UART_LSR) & UART_LSR_THRE))
1828 : break;
1829 9656 : } while (--count > 0);
1830 :
1831 712 : if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1832 712 : uart_write_wakeup(port);
1833 :
1834 : /*
1835 : * With RPM enabled, we have to wait until the FIFO is empty before the
1836 : * HW can go idle. So we get here once again with empty FIFO and disable
1837 : * the interrupt and RPM in __stop_tx()
1838 : */
1839 712 : if (uart_circ_empty(xmit) && !(up->capabilities & UART_CAP_RPM))
1840 170 : __stop_tx(up);
1841 : }
1842 : EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1843 :
1844 : /* Caller holds uart port lock */
1845 750 : unsigned int serial8250_modem_status(struct uart_8250_port *up)
1846 : {
1847 750 : struct uart_port *port = &up->port;
1848 750 : unsigned int status = serial_in(up, UART_MSR);
1849 :
1850 750 : status |= up->msr_saved_flags;
1851 750 : up->msr_saved_flags = 0;
1852 750 : if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1853 0 : port->state != NULL) {
1854 0 : if (status & UART_MSR_TERI)
1855 0 : port->icount.rng++;
1856 0 : if (status & UART_MSR_DDSR)
1857 0 : port->icount.dsr++;
1858 0 : if (status & UART_MSR_DDCD)
1859 0 : uart_handle_dcd_change(port, status & UART_MSR_DCD);
1860 0 : if (status & UART_MSR_DCTS)
1861 0 : uart_handle_cts_change(port, status & UART_MSR_CTS);
1862 :
1863 0 : wake_up_interruptible(&port->state->port.delta_msr_wait);
1864 : }
1865 :
1866 750 : return status;
1867 : }
1868 : EXPORT_SYMBOL_GPL(serial8250_modem_status);
1869 :
1870 0 : static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1871 : {
1872 0 : switch (iir & 0x3f) {
1873 : case UART_IIR_RX_TIMEOUT:
1874 0 : serial8250_rx_dma_flush(up);
1875 : fallthrough;
1876 : case UART_IIR_RLSI:
1877 : return true;
1878 : }
1879 0 : return up->dma->rx_dma(up);
1880 : }
1881 :
1882 : /*
1883 : * This handles the interrupt from one port.
1884 : */
1885 1129 : int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1886 : {
1887 1129 : unsigned char status;
1888 1129 : unsigned long flags;
1889 1129 : struct uart_8250_port *up = up_to_u8250p(port);
1890 1129 : bool skip_rx = false;
1891 :
1892 1129 : if (iir & UART_IIR_NO_INT)
1893 : return 0;
1894 :
1895 750 : spin_lock_irqsave(&port->lock, flags);
1896 :
1897 750 : status = serial_port_in(port, UART_LSR);
1898 :
1899 : /*
1900 : * If port is stopped and there are no error conditions in the
1901 : * FIFO, then don't drain the FIFO, as this may lead to TTY buffer
1902 : * overflow. Not servicing, RX FIFO would trigger auto HW flow
1903 : * control when FIFO occupancy reaches preset threshold, thus
1904 : * halting RX. This only works when auto HW flow control is
1905 : * available.
1906 : */
1907 750 : if (!(status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS)) &&
1908 750 : (port->status & (UPSTAT_AUTOCTS | UPSTAT_AUTORTS)) &&
1909 0 : !(port->read_status_mask & UART_LSR_DR))
1910 : skip_rx = true;
1911 :
1912 750 : if (status & (UART_LSR_DR | UART_LSR_BI) && !skip_rx) {
1913 0 : if (!up->dma || handle_rx_dma(up, iir))
1914 0 : status = serial8250_rx_chars(up, status);
1915 : }
1916 750 : serial8250_modem_status(up);
1917 750 : if ((!up->dma || up->dma->tx_err) && (status & UART_LSR_THRE) &&
1918 750 : (up->ier & UART_IER_THRI))
1919 750 : serial8250_tx_chars(up);
1920 :
1921 750 : uart_unlock_and_check_sysrq(port, flags);
1922 750 : return 1;
1923 : }
1924 : EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1925 :
1926 1129 : static int serial8250_default_handle_irq(struct uart_port *port)
1927 : {
1928 1129 : struct uart_8250_port *up = up_to_u8250p(port);
1929 1129 : unsigned int iir;
1930 1129 : int ret;
1931 :
1932 1129 : serial8250_rpm_get(up);
1933 :
1934 1129 : iir = serial_port_in(port, UART_IIR);
1935 1129 : ret = serial8250_handle_irq(port, iir);
1936 :
1937 1129 : serial8250_rpm_put(up);
1938 1129 : return ret;
1939 : }
1940 :
1941 : /*
1942 : * Newer 16550 compatible parts such as the SC16C650 & Altera 16550 Soft IP
1943 : * have a programmable TX threshold that triggers the THRE interrupt in
1944 : * the IIR register. In this case, the THRE interrupt indicates the FIFO
1945 : * has space available. Load it up with tx_loadsz bytes.
1946 : */
1947 0 : static int serial8250_tx_threshold_handle_irq(struct uart_port *port)
1948 : {
1949 0 : unsigned long flags;
1950 0 : unsigned int iir = serial_port_in(port, UART_IIR);
1951 :
1952 : /* TX Threshold IRQ triggered so load up FIFO */
1953 0 : if ((iir & UART_IIR_ID) == UART_IIR_THRI) {
1954 0 : struct uart_8250_port *up = up_to_u8250p(port);
1955 :
1956 0 : spin_lock_irqsave(&port->lock, flags);
1957 0 : serial8250_tx_chars(up);
1958 0 : spin_unlock_irqrestore(&port->lock, flags);
1959 : }
1960 :
1961 0 : iir = serial_port_in(port, UART_IIR);
1962 0 : return serial8250_handle_irq(port, iir);
1963 : }
1964 :
1965 135 : static unsigned int serial8250_tx_empty(struct uart_port *port)
1966 : {
1967 135 : struct uart_8250_port *up = up_to_u8250p(port);
1968 135 : unsigned long flags;
1969 135 : unsigned int lsr;
1970 :
1971 135 : serial8250_rpm_get(up);
1972 :
1973 135 : spin_lock_irqsave(&port->lock, flags);
1974 135 : lsr = serial_port_in(port, UART_LSR);
1975 135 : up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1976 135 : spin_unlock_irqrestore(&port->lock, flags);
1977 :
1978 135 : serial8250_rpm_put(up);
1979 :
1980 135 : return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1981 : }
1982 :
1983 0 : unsigned int serial8250_do_get_mctrl(struct uart_port *port)
1984 : {
1985 0 : struct uart_8250_port *up = up_to_u8250p(port);
1986 0 : unsigned int status;
1987 0 : unsigned int val;
1988 :
1989 0 : serial8250_rpm_get(up);
1990 0 : status = serial8250_modem_status(up);
1991 0 : serial8250_rpm_put(up);
1992 :
1993 0 : val = serial8250_MSR_to_TIOCM(status);
1994 0 : if (up->gpios)
1995 : return mctrl_gpio_get(up->gpios, &val);
1996 :
1997 : return val;
1998 : }
1999 : EXPORT_SYMBOL_GPL(serial8250_do_get_mctrl);
2000 :
2001 0 : static unsigned int serial8250_get_mctrl(struct uart_port *port)
2002 : {
2003 0 : if (port->get_mctrl)
2004 0 : return port->get_mctrl(port);
2005 0 : return serial8250_do_get_mctrl(port);
2006 : }
2007 :
2008 5 : void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl)
2009 : {
2010 5 : struct uart_8250_port *up = up_to_u8250p(port);
2011 5 : unsigned char mcr;
2012 :
2013 5 : if (port->rs485.flags & SER_RS485_ENABLED) {
2014 0 : if (serial8250_in_MCR(up) & UART_MCR_RTS)
2015 0 : mctrl |= TIOCM_RTS;
2016 : else
2017 0 : mctrl &= ~TIOCM_RTS;
2018 : }
2019 :
2020 5 : mcr = serial8250_TIOCM_to_MCR(mctrl);
2021 :
2022 5 : mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
2023 :
2024 5 : serial8250_out_MCR(up, mcr);
2025 5 : }
2026 : EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl);
2027 :
2028 5 : static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
2029 : {
2030 5 : if (port->set_mctrl)
2031 0 : port->set_mctrl(port, mctrl);
2032 : else
2033 5 : serial8250_do_set_mctrl(port, mctrl);
2034 5 : }
2035 :
2036 0 : static void serial8250_break_ctl(struct uart_port *port, int break_state)
2037 : {
2038 0 : struct uart_8250_port *up = up_to_u8250p(port);
2039 0 : unsigned long flags;
2040 :
2041 0 : serial8250_rpm_get(up);
2042 0 : spin_lock_irqsave(&port->lock, flags);
2043 0 : if (break_state == -1)
2044 0 : up->lcr |= UART_LCR_SBC;
2045 : else
2046 0 : up->lcr &= ~UART_LCR_SBC;
2047 0 : serial_port_out(port, UART_LCR, up->lcr);
2048 0 : spin_unlock_irqrestore(&port->lock, flags);
2049 0 : serial8250_rpm_put(up);
2050 0 : }
2051 :
2052 : /*
2053 : * Wait for transmitter & holding register to empty
2054 : */
2055 13940 : static void wait_for_xmitr(struct uart_8250_port *up, int bits)
2056 : {
2057 13940 : unsigned int status, tmout = 10000;
2058 :
2059 : /* Wait up to 10ms for the character(s) to be sent. */
2060 13940 : for (;;) {
2061 13940 : status = serial_in(up, UART_LSR);
2062 :
2063 13940 : up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
2064 :
2065 13940 : if ((status & bits) == bits)
2066 : break;
2067 0 : if (--tmout == 0)
2068 : break;
2069 0 : udelay(1);
2070 0 : touch_nmi_watchdog();
2071 : }
2072 :
2073 : /* Wait up to 1s for flow control if necessary */
2074 13940 : if (up->port.flags & UPF_CONS_FLOW) {
2075 0 : for (tmout = 1000000; tmout; tmout--) {
2076 0 : unsigned int msr = serial_in(up, UART_MSR);
2077 0 : up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
2078 0 : if (msr & UART_MSR_CTS)
2079 : break;
2080 0 : udelay(1);
2081 0 : touch_nmi_watchdog();
2082 : }
2083 : }
2084 13940 : }
2085 :
2086 : #ifdef CONFIG_CONSOLE_POLL
2087 : /*
2088 : * Console polling routines for writing and reading from the uart while
2089 : * in an interrupt or debug context.
2090 : */
2091 :
2092 : static int serial8250_get_poll_char(struct uart_port *port)
2093 : {
2094 : struct uart_8250_port *up = up_to_u8250p(port);
2095 : unsigned char lsr;
2096 : int status;
2097 :
2098 : serial8250_rpm_get(up);
2099 :
2100 : lsr = serial_port_in(port, UART_LSR);
2101 :
2102 : if (!(lsr & UART_LSR_DR)) {
2103 : status = NO_POLL_CHAR;
2104 : goto out;
2105 : }
2106 :
2107 : status = serial_port_in(port, UART_RX);
2108 : out:
2109 : serial8250_rpm_put(up);
2110 : return status;
2111 : }
2112 :
2113 :
2114 : static void serial8250_put_poll_char(struct uart_port *port,
2115 : unsigned char c)
2116 : {
2117 : unsigned int ier;
2118 : struct uart_8250_port *up = up_to_u8250p(port);
2119 :
2120 : serial8250_rpm_get(up);
2121 : /*
2122 : * First save the IER then disable the interrupts
2123 : */
2124 : ier = serial_port_in(port, UART_IER);
2125 : if (up->capabilities & UART_CAP_UUE)
2126 : serial_port_out(port, UART_IER, UART_IER_UUE);
2127 : else
2128 : serial_port_out(port, UART_IER, 0);
2129 :
2130 : wait_for_xmitr(up, BOTH_EMPTY);
2131 : /*
2132 : * Send the character out.
2133 : */
2134 : serial_port_out(port, UART_TX, c);
2135 :
2136 : /*
2137 : * Finally, wait for transmitter to become empty
2138 : * and restore the IER
2139 : */
2140 : wait_for_xmitr(up, BOTH_EMPTY);
2141 : serial_port_out(port, UART_IER, ier);
2142 : serial8250_rpm_put(up);
2143 : }
2144 :
2145 : #endif /* CONFIG_CONSOLE_POLL */
2146 :
2147 1 : int serial8250_do_startup(struct uart_port *port)
2148 : {
2149 1 : struct uart_8250_port *up = up_to_u8250p(port);
2150 1 : unsigned long flags;
2151 1 : unsigned char lsr, iir;
2152 1 : int retval;
2153 :
2154 1 : if (!port->fifosize)
2155 0 : port->fifosize = uart_config[port->type].fifo_size;
2156 1 : if (!up->tx_loadsz)
2157 0 : up->tx_loadsz = uart_config[port->type].tx_loadsz;
2158 1 : if (!up->capabilities)
2159 0 : up->capabilities = uart_config[port->type].flags;
2160 1 : up->mcr = 0;
2161 :
2162 1 : if (port->iotype != up->cur_iotype)
2163 0 : set_io_from_upio(port);
2164 :
2165 1 : serial8250_rpm_get(up);
2166 1 : if (port->type == PORT_16C950) {
2167 : /* Wake up and initialize UART */
2168 0 : up->acr = 0;
2169 0 : serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2170 0 : serial_port_out(port, UART_EFR, UART_EFR_ECB);
2171 0 : serial_port_out(port, UART_IER, 0);
2172 0 : serial_port_out(port, UART_LCR, 0);
2173 0 : serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2174 0 : serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2175 0 : serial_port_out(port, UART_EFR, UART_EFR_ECB);
2176 0 : serial_port_out(port, UART_LCR, 0);
2177 : }
2178 :
2179 1 : if (port->type == PORT_DA830) {
2180 : /* Reset the port */
2181 0 : serial_port_out(port, UART_IER, 0);
2182 0 : serial_port_out(port, UART_DA830_PWREMU_MGMT, 0);
2183 0 : mdelay(10);
2184 :
2185 : /* Enable Tx, Rx and free run mode */
2186 0 : serial_port_out(port, UART_DA830_PWREMU_MGMT,
2187 : UART_DA830_PWREMU_MGMT_UTRST |
2188 : UART_DA830_PWREMU_MGMT_URRST |
2189 : UART_DA830_PWREMU_MGMT_FREE);
2190 : }
2191 :
2192 1 : if (port->type == PORT_NPCM) {
2193 : /*
2194 : * Nuvoton calls the scratch register 'UART_TOR' (timeout
2195 : * register). Enable it, and set TIOC (timeout interrupt
2196 : * comparator) to be 0x20 for correct operation.
2197 : */
2198 0 : serial_port_out(port, UART_NPCM_TOR, UART_NPCM_TOIE | 0x20);
2199 : }
2200 :
2201 : #ifdef CONFIG_SERIAL_8250_RSA
2202 : /*
2203 : * If this is an RSA port, see if we can kick it up to the
2204 : * higher speed clock.
2205 : */
2206 : enable_rsa(up);
2207 : #endif
2208 :
2209 : /*
2210 : * Clear the FIFO buffers and disable them.
2211 : * (they will be reenabled in set_termios())
2212 : */
2213 1 : serial8250_clear_fifos(up);
2214 :
2215 : /*
2216 : * Clear the interrupt registers.
2217 : */
2218 1 : serial_port_in(port, UART_LSR);
2219 1 : serial_port_in(port, UART_RX);
2220 1 : serial_port_in(port, UART_IIR);
2221 1 : serial_port_in(port, UART_MSR);
2222 :
2223 : /*
2224 : * At this point, there's no way the LSR could still be 0xff;
2225 : * if it is, then bail out, because there's likely no UART
2226 : * here.
2227 : */
2228 1 : if (!(port->flags & UPF_BUGGY_UART) &&
2229 1 : (serial_port_in(port, UART_LSR) == 0xff)) {
2230 0 : dev_info_ratelimited(port->dev, "LSR safety check engaged!\n");
2231 0 : retval = -ENODEV;
2232 0 : goto out;
2233 : }
2234 :
2235 : /*
2236 : * For a XR16C850, we need to set the trigger levels
2237 : */
2238 1 : if (port->type == PORT_16850) {
2239 0 : unsigned char fctr;
2240 :
2241 0 : serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2242 :
2243 0 : fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2244 0 : serial_port_out(port, UART_FCTR,
2245 : fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2246 0 : serial_port_out(port, UART_TRG, UART_TRG_96);
2247 0 : serial_port_out(port, UART_FCTR,
2248 : fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2249 0 : serial_port_out(port, UART_TRG, UART_TRG_96);
2250 :
2251 0 : serial_port_out(port, UART_LCR, 0);
2252 : }
2253 :
2254 : /*
2255 : * For the Altera 16550 variants, set TX threshold trigger level.
2256 : */
2257 1 : if (((port->type == PORT_ALTR_16550_F32) ||
2258 1 : (port->type == PORT_ALTR_16550_F64) ||
2259 0 : (port->type == PORT_ALTR_16550_F128)) && (port->fifosize > 1)) {
2260 : /* Bounds checking of TX threshold (valid 0 to fifosize-2) */
2261 0 : if ((up->tx_loadsz < 2) || (up->tx_loadsz > port->fifosize)) {
2262 0 : dev_err(port->dev, "TX FIFO Threshold errors, skipping\n");
2263 : } else {
2264 0 : serial_port_out(port, UART_ALTR_AFR,
2265 : UART_ALTR_EN_TXFIFO_LW);
2266 0 : serial_port_out(port, UART_ALTR_TX_LOW,
2267 0 : port->fifosize - up->tx_loadsz);
2268 0 : port->handle_irq = serial8250_tx_threshold_handle_irq;
2269 : }
2270 : }
2271 :
2272 : /* Check if we need to have shared IRQs */
2273 1 : if (port->irq && (up->port.flags & UPF_SHARE_IRQ))
2274 0 : up->port.irqflags |= IRQF_SHARED;
2275 :
2276 1 : if (port->irq && !(up->port.flags & UPF_NO_THRE_TEST)) {
2277 1 : unsigned char iir1;
2278 :
2279 1 : if (port->irqflags & IRQF_SHARED)
2280 0 : disable_irq_nosync(port->irq);
2281 :
2282 : /*
2283 : * Test for UARTs that do not reassert THRE when the
2284 : * transmitter is idle and the interrupt has already
2285 : * been cleared. Real 16550s should always reassert
2286 : * this interrupt whenever the transmitter is idle and
2287 : * the interrupt is enabled. Delays are necessary to
2288 : * allow register changes to become visible.
2289 : */
2290 1 : spin_lock_irqsave(&port->lock, flags);
2291 :
2292 1 : wait_for_xmitr(up, UART_LSR_THRE);
2293 1 : serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2294 1 : udelay(1); /* allow THRE to set */
2295 1 : iir1 = serial_port_in(port, UART_IIR);
2296 1 : serial_port_out(port, UART_IER, 0);
2297 1 : serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2298 1 : udelay(1); /* allow a working UART time to re-assert THRE */
2299 1 : iir = serial_port_in(port, UART_IIR);
2300 1 : serial_port_out(port, UART_IER, 0);
2301 :
2302 1 : spin_unlock_irqrestore(&port->lock, flags);
2303 :
2304 1 : if (port->irqflags & IRQF_SHARED)
2305 0 : enable_irq(port->irq);
2306 :
2307 : /*
2308 : * If the interrupt is not reasserted, or we otherwise
2309 : * don't trust the iir, setup a timer to kick the UART
2310 : * on a regular basis.
2311 : */
2312 1 : if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2313 1 : up->port.flags & UPF_BUG_THRE) {
2314 0 : up->bugs |= UART_BUG_THRE;
2315 : }
2316 : }
2317 :
2318 1 : retval = up->ops->setup_irq(up);
2319 1 : if (retval)
2320 0 : goto out;
2321 :
2322 : /*
2323 : * Now, initialize the UART
2324 : */
2325 1 : serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
2326 :
2327 1 : spin_lock_irqsave(&port->lock, flags);
2328 1 : if (up->port.flags & UPF_FOURPORT) {
2329 0 : if (!up->port.irq)
2330 0 : up->port.mctrl |= TIOCM_OUT1;
2331 : } else
2332 : /*
2333 : * Most PC uarts need OUT2 raised to enable interrupts.
2334 : */
2335 1 : if (port->irq)
2336 1 : up->port.mctrl |= TIOCM_OUT2;
2337 :
2338 1 : serial8250_set_mctrl(port, port->mctrl);
2339 :
2340 : /*
2341 : * Serial over Lan (SoL) hack:
2342 : * Intel 8257x Gigabit ethernet chips have a 16550 emulation, to be
2343 : * used for Serial Over Lan. Those chips take a longer time than a
2344 : * normal serial device to signalize that a transmission data was
2345 : * queued. Due to that, the above test generally fails. One solution
2346 : * would be to delay the reading of iir. However, this is not
2347 : * reliable, since the timeout is variable. So, let's just don't
2348 : * test if we receive TX irq. This way, we'll never enable
2349 : * UART_BUG_TXEN.
2350 : */
2351 1 : if (up->port.quirks & UPQ_NO_TXEN_TEST)
2352 0 : goto dont_test_tx_en;
2353 :
2354 : /*
2355 : * Do a quick test to see if we receive an interrupt when we enable
2356 : * the TX irq.
2357 : */
2358 1 : serial_port_out(port, UART_IER, UART_IER_THRI);
2359 1 : lsr = serial_port_in(port, UART_LSR);
2360 1 : iir = serial_port_in(port, UART_IIR);
2361 1 : serial_port_out(port, UART_IER, 0);
2362 :
2363 1 : if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2364 0 : if (!(up->bugs & UART_BUG_TXEN)) {
2365 0 : up->bugs |= UART_BUG_TXEN;
2366 0 : dev_dbg(port->dev, "enabling bad tx status workarounds\n");
2367 : }
2368 : } else {
2369 1 : up->bugs &= ~UART_BUG_TXEN;
2370 : }
2371 :
2372 1 : dont_test_tx_en:
2373 1 : spin_unlock_irqrestore(&port->lock, flags);
2374 :
2375 : /*
2376 : * Clear the interrupt registers again for luck, and clear the
2377 : * saved flags to avoid getting false values from polling
2378 : * routines or the previous session.
2379 : */
2380 1 : serial_port_in(port, UART_LSR);
2381 1 : serial_port_in(port, UART_RX);
2382 1 : serial_port_in(port, UART_IIR);
2383 1 : serial_port_in(port, UART_MSR);
2384 1 : up->lsr_saved_flags = 0;
2385 1 : up->msr_saved_flags = 0;
2386 :
2387 : /*
2388 : * Request DMA channels for both RX and TX.
2389 : */
2390 1 : if (up->dma) {
2391 0 : const char *msg = NULL;
2392 :
2393 0 : if (uart_console(port))
2394 : msg = "forbid DMA for kernel console";
2395 0 : else if (serial8250_request_dma(up))
2396 0 : msg = "failed to request DMA";
2397 0 : if (msg) {
2398 0 : dev_warn_ratelimited(port->dev, "%s\n", msg);
2399 0 : up->dma = NULL;
2400 : }
2401 : }
2402 :
2403 : /*
2404 : * Set the IER shadow for rx interrupts but defer actual interrupt
2405 : * enable until after the FIFOs are enabled; otherwise, an already-
2406 : * active sender can swamp the interrupt handler with "too much work".
2407 : */
2408 1 : up->ier = UART_IER_RLSI | UART_IER_RDI;
2409 :
2410 1 : if (port->flags & UPF_FOURPORT) {
2411 0 : unsigned int icp;
2412 : /*
2413 : * Enable interrupts on the AST Fourport board
2414 : */
2415 0 : icp = (port->iobase & 0xfe0) | 0x01f;
2416 0 : outb_p(0x80, icp);
2417 0 : inb_p(icp);
2418 : }
2419 : retval = 0;
2420 1 : out:
2421 1 : serial8250_rpm_put(up);
2422 1 : return retval;
2423 : }
2424 : EXPORT_SYMBOL_GPL(serial8250_do_startup);
2425 :
2426 1 : static int serial8250_startup(struct uart_port *port)
2427 : {
2428 1 : if (port->startup)
2429 0 : return port->startup(port);
2430 1 : return serial8250_do_startup(port);
2431 : }
2432 :
2433 0 : void serial8250_do_shutdown(struct uart_port *port)
2434 : {
2435 0 : struct uart_8250_port *up = up_to_u8250p(port);
2436 0 : unsigned long flags;
2437 :
2438 0 : serial8250_rpm_get(up);
2439 : /*
2440 : * Disable interrupts from this port
2441 : */
2442 0 : spin_lock_irqsave(&port->lock, flags);
2443 0 : up->ier = 0;
2444 0 : serial_port_out(port, UART_IER, 0);
2445 0 : spin_unlock_irqrestore(&port->lock, flags);
2446 :
2447 0 : synchronize_irq(port->irq);
2448 :
2449 0 : if (up->dma)
2450 0 : serial8250_release_dma(up);
2451 :
2452 0 : spin_lock_irqsave(&port->lock, flags);
2453 0 : if (port->flags & UPF_FOURPORT) {
2454 : /* reset interrupts on the AST Fourport board */
2455 0 : inb((port->iobase & 0xfe0) | 0x1f);
2456 0 : port->mctrl |= TIOCM_OUT1;
2457 : } else
2458 0 : port->mctrl &= ~TIOCM_OUT2;
2459 :
2460 0 : serial8250_set_mctrl(port, port->mctrl);
2461 0 : spin_unlock_irqrestore(&port->lock, flags);
2462 :
2463 : /*
2464 : * Disable break condition and FIFOs
2465 : */
2466 0 : serial_port_out(port, UART_LCR,
2467 0 : serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2468 0 : serial8250_clear_fifos(up);
2469 :
2470 : #ifdef CONFIG_SERIAL_8250_RSA
2471 : /*
2472 : * Reset the RSA board back to 115kbps compat mode.
2473 : */
2474 : disable_rsa(up);
2475 : #endif
2476 :
2477 : /*
2478 : * Read data port to reset things, and then unlink from
2479 : * the IRQ chain.
2480 : */
2481 0 : serial_port_in(port, UART_RX);
2482 0 : serial8250_rpm_put(up);
2483 :
2484 0 : up->ops->release_irq(up);
2485 0 : }
2486 : EXPORT_SYMBOL_GPL(serial8250_do_shutdown);
2487 :
2488 0 : static void serial8250_shutdown(struct uart_port *port)
2489 : {
2490 0 : if (port->shutdown)
2491 0 : port->shutdown(port);
2492 : else
2493 0 : serial8250_do_shutdown(port);
2494 0 : }
2495 :
2496 : /* Nuvoton NPCM UARTs have a custom divisor calculation */
2497 0 : static unsigned int npcm_get_divisor(struct uart_8250_port *up,
2498 : unsigned int baud)
2499 : {
2500 0 : struct uart_port *port = &up->port;
2501 :
2502 0 : return DIV_ROUND_CLOSEST(port->uartclk, 16 * baud + 2) - 2;
2503 : }
2504 :
2505 2 : static unsigned int serial8250_do_get_divisor(struct uart_port *port,
2506 : unsigned int baud,
2507 : unsigned int *frac)
2508 : {
2509 2 : struct uart_8250_port *up = up_to_u8250p(port);
2510 2 : unsigned int quot;
2511 :
2512 : /*
2513 : * Handle magic divisors for baud rates above baud_base on
2514 : * SMSC SuperIO chips.
2515 : *
2516 : */
2517 2 : if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2518 0 : baud == (port->uartclk/4))
2519 : quot = 0x8001;
2520 2 : else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2521 0 : baud == (port->uartclk/8))
2522 : quot = 0x8002;
2523 2 : else if (up->port.type == PORT_NPCM)
2524 0 : quot = npcm_get_divisor(up, baud);
2525 : else
2526 2 : quot = uart_get_divisor(port, baud);
2527 :
2528 : /*
2529 : * Oxford Semi 952 rev B workaround
2530 : */
2531 2 : if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2532 0 : quot++;
2533 :
2534 2 : return quot;
2535 : }
2536 :
2537 2 : static unsigned int serial8250_get_divisor(struct uart_port *port,
2538 : unsigned int baud,
2539 : unsigned int *frac)
2540 : {
2541 2 : if (port->get_divisor)
2542 0 : return port->get_divisor(port, baud, frac);
2543 :
2544 2 : return serial8250_do_get_divisor(port, baud, frac);
2545 : }
2546 :
2547 2 : static unsigned char serial8250_compute_lcr(struct uart_8250_port *up,
2548 : tcflag_t c_cflag)
2549 : {
2550 2 : unsigned char cval;
2551 :
2552 2 : switch (c_cflag & CSIZE) {
2553 : case CS5:
2554 : cval = UART_LCR_WLEN5;
2555 : break;
2556 0 : case CS6:
2557 0 : cval = UART_LCR_WLEN6;
2558 0 : break;
2559 0 : case CS7:
2560 0 : cval = UART_LCR_WLEN7;
2561 0 : break;
2562 2 : default:
2563 : case CS8:
2564 2 : cval = UART_LCR_WLEN8;
2565 2 : break;
2566 : }
2567 :
2568 2 : if (c_cflag & CSTOPB)
2569 0 : cval |= UART_LCR_STOP;
2570 2 : if (c_cflag & PARENB) {
2571 0 : cval |= UART_LCR_PARITY;
2572 0 : if (up->bugs & UART_BUG_PARITY)
2573 0 : up->fifo_bug = true;
2574 : }
2575 2 : if (!(c_cflag & PARODD))
2576 2 : cval |= UART_LCR_EPAR;
2577 : #ifdef CMSPAR
2578 2 : if (c_cflag & CMSPAR)
2579 0 : cval |= UART_LCR_SPAR;
2580 : #endif
2581 :
2582 2 : return cval;
2583 : }
2584 :
2585 2 : void serial8250_do_set_divisor(struct uart_port *port, unsigned int baud,
2586 : unsigned int quot, unsigned int quot_frac)
2587 : {
2588 2 : struct uart_8250_port *up = up_to_u8250p(port);
2589 :
2590 : /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2591 2 : if (is_omap1510_8250(up)) {
2592 : if (baud == 115200) {
2593 : quot = 1;
2594 2 : serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2595 : } else
2596 2 : serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2597 : }
2598 :
2599 : /*
2600 : * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2601 : * otherwise just set DLAB
2602 : */
2603 2 : if (up->capabilities & UART_NATSEMI)
2604 0 : serial_port_out(port, UART_LCR, 0xe0);
2605 : else
2606 2 : serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB);
2607 :
2608 2 : serial_dl_write(up, quot);
2609 2 : }
2610 : EXPORT_SYMBOL_GPL(serial8250_do_set_divisor);
2611 :
2612 2 : static void serial8250_set_divisor(struct uart_port *port, unsigned int baud,
2613 : unsigned int quot, unsigned int quot_frac)
2614 : {
2615 2 : if (port->set_divisor)
2616 0 : port->set_divisor(port, baud, quot, quot_frac);
2617 : else
2618 2 : serial8250_do_set_divisor(port, baud, quot, quot_frac);
2619 2 : }
2620 :
2621 2 : static unsigned int serial8250_get_baud_rate(struct uart_port *port,
2622 : struct ktermios *termios,
2623 : struct ktermios *old)
2624 : {
2625 2 : unsigned int tolerance = port->uartclk / 100;
2626 :
2627 : /*
2628 : * Ask the core to calculate the divisor for us.
2629 : * Allow 1% tolerance at the upper limit so uart clks marginally
2630 : * slower than nominal still match standard baud rates without
2631 : * causing transmission errors.
2632 : */
2633 4 : return uart_get_baud_rate(port, termios, old,
2634 : port->uartclk / 16 / UART_DIV_MAX,
2635 2 : (port->uartclk + tolerance) / 16);
2636 : }
2637 :
2638 : /*
2639 : * Note in order to avoid the tty port mutex deadlock don't use the next method
2640 : * within the uart port callbacks. Primarily it's supposed to be utilized to
2641 : * handle a sudden reference clock rate change.
2642 : */
2643 0 : void serial8250_update_uartclk(struct uart_port *port, unsigned int uartclk)
2644 : {
2645 0 : struct uart_8250_port *up = up_to_u8250p(port);
2646 0 : unsigned int baud, quot, frac = 0;
2647 0 : struct ktermios *termios;
2648 0 : unsigned long flags;
2649 :
2650 0 : mutex_lock(&port->state->port.mutex);
2651 :
2652 0 : if (port->uartclk == uartclk)
2653 0 : goto out_lock;
2654 :
2655 0 : port->uartclk = uartclk;
2656 :
2657 0 : if (!tty_port_initialized(&port->state->port))
2658 0 : goto out_lock;
2659 :
2660 0 : termios = &port->state->port.tty->termios;
2661 :
2662 0 : baud = serial8250_get_baud_rate(port, termios, NULL);
2663 0 : quot = serial8250_get_divisor(port, baud, &frac);
2664 :
2665 0 : serial8250_rpm_get(up);
2666 0 : spin_lock_irqsave(&port->lock, flags);
2667 :
2668 0 : uart_update_timeout(port, termios->c_cflag, baud);
2669 :
2670 0 : serial8250_set_divisor(port, baud, quot, frac);
2671 0 : serial_port_out(port, UART_LCR, up->lcr);
2672 :
2673 0 : spin_unlock_irqrestore(&port->lock, flags);
2674 0 : serial8250_rpm_put(up);
2675 :
2676 0 : out_lock:
2677 0 : mutex_unlock(&port->state->port.mutex);
2678 0 : }
2679 : EXPORT_SYMBOL_GPL(serial8250_update_uartclk);
2680 :
2681 : void
2682 2 : serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2683 : struct ktermios *old)
2684 : {
2685 2 : struct uart_8250_port *up = up_to_u8250p(port);
2686 2 : unsigned char cval;
2687 2 : unsigned long flags;
2688 2 : unsigned int baud, quot, frac = 0;
2689 :
2690 2 : if (up->capabilities & UART_CAP_MINI) {
2691 0 : termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CMSPAR);
2692 0 : if ((termios->c_cflag & CSIZE) == CS5 ||
2693 : (termios->c_cflag & CSIZE) == CS6)
2694 0 : termios->c_cflag = (termios->c_cflag & ~CSIZE) | CS7;
2695 : }
2696 2 : cval = serial8250_compute_lcr(up, termios->c_cflag);
2697 :
2698 2 : baud = serial8250_get_baud_rate(port, termios, old);
2699 2 : quot = serial8250_get_divisor(port, baud, &frac);
2700 :
2701 : /*
2702 : * Ok, we're now changing the port state. Do it with
2703 : * interrupts disabled.
2704 : */
2705 2 : serial8250_rpm_get(up);
2706 2 : spin_lock_irqsave(&port->lock, flags);
2707 :
2708 2 : up->lcr = cval; /* Save computed LCR */
2709 :
2710 2 : if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2711 : /* NOTE: If fifo_bug is not set, a user can set RX_trigger. */
2712 1 : if ((baud < 2400 && !up->dma) || up->fifo_bug) {
2713 0 : up->fcr &= ~UART_FCR_TRIGGER_MASK;
2714 0 : up->fcr |= UART_FCR_TRIGGER_1;
2715 : }
2716 : }
2717 :
2718 : /*
2719 : * MCR-based auto flow control. When AFE is enabled, RTS will be
2720 : * deasserted when the receive FIFO contains more characters than
2721 : * the trigger, or the MCR RTS bit is cleared.
2722 : */
2723 2 : if (up->capabilities & UART_CAP_AFE) {
2724 0 : up->mcr &= ~UART_MCR_AFE;
2725 0 : if (termios->c_cflag & CRTSCTS)
2726 0 : up->mcr |= UART_MCR_AFE;
2727 : }
2728 :
2729 : /*
2730 : * Update the per-port timeout.
2731 : */
2732 2 : uart_update_timeout(port, termios->c_cflag, baud);
2733 :
2734 2 : port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2735 2 : if (termios->c_iflag & INPCK)
2736 0 : port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2737 2 : if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2738 0 : port->read_status_mask |= UART_LSR_BI;
2739 :
2740 : /*
2741 : * Characteres to ignore
2742 : */
2743 2 : port->ignore_status_mask = 0;
2744 2 : if (termios->c_iflag & IGNPAR)
2745 0 : port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2746 2 : if (termios->c_iflag & IGNBRK) {
2747 0 : port->ignore_status_mask |= UART_LSR_BI;
2748 : /*
2749 : * If we're ignoring parity and break indicators,
2750 : * ignore overruns too (for real raw support).
2751 : */
2752 0 : if (termios->c_iflag & IGNPAR)
2753 0 : port->ignore_status_mask |= UART_LSR_OE;
2754 : }
2755 :
2756 : /*
2757 : * ignore all characters if CREAD is not set
2758 : */
2759 2 : if ((termios->c_cflag & CREAD) == 0)
2760 0 : port->ignore_status_mask |= UART_LSR_DR;
2761 :
2762 : /*
2763 : * CTS flow control flag and modem status interrupts
2764 : */
2765 2 : up->ier &= ~UART_IER_MSI;
2766 2 : if (!(up->bugs & UART_BUG_NOMSR) &&
2767 2 : UART_ENABLE_MS(&up->port, termios->c_cflag))
2768 0 : up->ier |= UART_IER_MSI;
2769 2 : if (up->capabilities & UART_CAP_UUE)
2770 0 : up->ier |= UART_IER_UUE;
2771 2 : if (up->capabilities & UART_CAP_RTOIE)
2772 0 : up->ier |= UART_IER_RTOIE;
2773 :
2774 2 : serial_port_out(port, UART_IER, up->ier);
2775 :
2776 2 : if (up->capabilities & UART_CAP_EFR) {
2777 0 : unsigned char efr = 0;
2778 : /*
2779 : * TI16C752/Startech hardware flow control. FIXME:
2780 : * - TI16C752 requires control thresholds to be set.
2781 : * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2782 : */
2783 0 : if (termios->c_cflag & CRTSCTS)
2784 0 : efr |= UART_EFR_CTS;
2785 :
2786 0 : serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2787 0 : if (port->flags & UPF_EXAR_EFR)
2788 0 : serial_port_out(port, UART_XR_EFR, efr);
2789 : else
2790 0 : serial_port_out(port, UART_EFR, efr);
2791 : }
2792 :
2793 2 : serial8250_set_divisor(port, baud, quot, frac);
2794 :
2795 : /*
2796 : * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2797 : * is written without DLAB set, this mode will be disabled.
2798 : */
2799 2 : if (port->type == PORT_16750)
2800 0 : serial_port_out(port, UART_FCR, up->fcr);
2801 :
2802 2 : serial_port_out(port, UART_LCR, up->lcr); /* reset DLAB */
2803 2 : if (port->type != PORT_16750) {
2804 : /* emulated UARTs (Lucent Venus 167x) need two steps */
2805 2 : if (up->fcr & UART_FCR_ENABLE_FIFO)
2806 1 : serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2807 2 : serial_port_out(port, UART_FCR, up->fcr); /* set fcr */
2808 : }
2809 2 : serial8250_set_mctrl(port, port->mctrl);
2810 2 : spin_unlock_irqrestore(&port->lock, flags);
2811 2 : serial8250_rpm_put(up);
2812 :
2813 : /* Don't rewrite B0 */
2814 2 : if (tty_termios_baud_rate(termios))
2815 2 : tty_termios_encode_baud_rate(termios, baud, baud);
2816 2 : }
2817 : EXPORT_SYMBOL(serial8250_do_set_termios);
2818 :
2819 : static void
2820 2 : serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2821 : struct ktermios *old)
2822 : {
2823 2 : if (port->set_termios)
2824 0 : port->set_termios(port, termios, old);
2825 : else
2826 2 : serial8250_do_set_termios(port, termios, old);
2827 2 : }
2828 :
2829 0 : void serial8250_do_set_ldisc(struct uart_port *port, struct ktermios *termios)
2830 : {
2831 0 : if (termios->c_line == N_PPS) {
2832 0 : port->flags |= UPF_HARDPPS_CD;
2833 0 : spin_lock_irq(&port->lock);
2834 0 : serial8250_enable_ms(port);
2835 0 : spin_unlock_irq(&port->lock);
2836 : } else {
2837 0 : port->flags &= ~UPF_HARDPPS_CD;
2838 0 : if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2839 0 : spin_lock_irq(&port->lock);
2840 0 : serial8250_disable_ms(port);
2841 0 : spin_unlock_irq(&port->lock);
2842 : }
2843 : }
2844 0 : }
2845 : EXPORT_SYMBOL_GPL(serial8250_do_set_ldisc);
2846 :
2847 : static void
2848 0 : serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios)
2849 : {
2850 0 : if (port->set_ldisc)
2851 0 : port->set_ldisc(port, termios);
2852 : else
2853 0 : serial8250_do_set_ldisc(port, termios);
2854 0 : }
2855 :
2856 1 : void serial8250_do_pm(struct uart_port *port, unsigned int state,
2857 : unsigned int oldstate)
2858 : {
2859 0 : struct uart_8250_port *p = up_to_u8250p(port);
2860 :
2861 1 : serial8250_set_sleep(p, state != 0);
2862 1 : }
2863 : EXPORT_SYMBOL(serial8250_do_pm);
2864 :
2865 : static void
2866 1 : serial8250_pm(struct uart_port *port, unsigned int state,
2867 : unsigned int oldstate)
2868 : {
2869 1 : if (port->pm)
2870 0 : port->pm(port, state, oldstate);
2871 : else
2872 1 : serial8250_do_pm(port, state, oldstate);
2873 1 : }
2874 :
2875 7 : static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2876 : {
2877 7 : if (pt->port.mapsize)
2878 0 : return pt->port.mapsize;
2879 7 : if (pt->port.iotype == UPIO_AU) {
2880 0 : if (pt->port.type == PORT_RT2880)
2881 : return 0x100;
2882 0 : return 0x1000;
2883 : }
2884 7 : if (is_omap1_8250(pt))
2885 : return 0x16 << pt->port.regshift;
2886 :
2887 7 : return 8 << pt->port.regshift;
2888 : }
2889 :
2890 : /*
2891 : * Resource handling.
2892 : */
2893 4 : static int serial8250_request_std_resource(struct uart_8250_port *up)
2894 : {
2895 4 : unsigned int size = serial8250_port_size(up);
2896 4 : struct uart_port *port = &up->port;
2897 4 : int ret = 0;
2898 :
2899 4 : switch (port->iotype) {
2900 0 : case UPIO_AU:
2901 : case UPIO_TSI:
2902 : case UPIO_MEM32:
2903 : case UPIO_MEM32BE:
2904 : case UPIO_MEM16:
2905 : case UPIO_MEM:
2906 0 : if (!port->mapbase)
2907 : break;
2908 :
2909 0 : if (!request_mem_region(port->mapbase, size, "serial")) {
2910 : ret = -EBUSY;
2911 : break;
2912 : }
2913 :
2914 0 : if (port->flags & UPF_IOREMAP) {
2915 0 : port->membase = ioremap(port->mapbase, size);
2916 0 : if (!port->membase) {
2917 0 : release_mem_region(port->mapbase, size);
2918 0 : ret = -ENOMEM;
2919 : }
2920 : }
2921 : break;
2922 :
2923 4 : case UPIO_HUB6:
2924 : case UPIO_PORT:
2925 4 : if (!request_region(port->iobase, size, "serial"))
2926 0 : ret = -EBUSY;
2927 : break;
2928 : }
2929 0 : return ret;
2930 : }
2931 :
2932 3 : static void serial8250_release_std_resource(struct uart_8250_port *up)
2933 : {
2934 3 : unsigned int size = serial8250_port_size(up);
2935 3 : struct uart_port *port = &up->port;
2936 :
2937 3 : switch (port->iotype) {
2938 0 : case UPIO_AU:
2939 : case UPIO_TSI:
2940 : case UPIO_MEM32:
2941 : case UPIO_MEM32BE:
2942 : case UPIO_MEM16:
2943 : case UPIO_MEM:
2944 0 : if (!port->mapbase)
2945 : break;
2946 :
2947 0 : if (port->flags & UPF_IOREMAP) {
2948 0 : iounmap(port->membase);
2949 0 : port->membase = NULL;
2950 : }
2951 :
2952 0 : release_mem_region(port->mapbase, size);
2953 0 : break;
2954 :
2955 3 : case UPIO_HUB6:
2956 : case UPIO_PORT:
2957 3 : release_region(port->iobase, size);
2958 3 : break;
2959 : }
2960 0 : }
2961 :
2962 0 : static void serial8250_release_port(struct uart_port *port)
2963 : {
2964 0 : struct uart_8250_port *up = up_to_u8250p(port);
2965 :
2966 0 : serial8250_release_std_resource(up);
2967 0 : }
2968 :
2969 0 : static int serial8250_request_port(struct uart_port *port)
2970 : {
2971 0 : struct uart_8250_port *up = up_to_u8250p(port);
2972 :
2973 0 : return serial8250_request_std_resource(up);
2974 : }
2975 :
2976 0 : static int fcr_get_rxtrig_bytes(struct uart_8250_port *up)
2977 : {
2978 0 : const struct serial8250_config *conf_type = &uart_config[up->port.type];
2979 0 : unsigned char bytes;
2980 :
2981 0 : bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)];
2982 :
2983 0 : return bytes ? bytes : -EOPNOTSUPP;
2984 : }
2985 :
2986 0 : static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes)
2987 : {
2988 0 : const struct serial8250_config *conf_type = &uart_config[up->port.type];
2989 0 : int i;
2990 :
2991 0 : if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)])
2992 : return -EOPNOTSUPP;
2993 :
2994 0 : for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) {
2995 0 : if (bytes < conf_type->rxtrig_bytes[i])
2996 : /* Use the nearest lower value */
2997 0 : return (--i) << UART_FCR_R_TRIG_SHIFT;
2998 : }
2999 :
3000 : return UART_FCR_R_TRIG_11;
3001 : }
3002 :
3003 0 : static int do_get_rxtrig(struct tty_port *port)
3004 : {
3005 0 : struct uart_state *state = container_of(port, struct uart_state, port);
3006 0 : struct uart_port *uport = state->uart_port;
3007 0 : struct uart_8250_port *up = up_to_u8250p(uport);
3008 :
3009 0 : if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
3010 : return -EINVAL;
3011 :
3012 0 : return fcr_get_rxtrig_bytes(up);
3013 : }
3014 :
3015 0 : static int do_serial8250_get_rxtrig(struct tty_port *port)
3016 : {
3017 0 : int rxtrig_bytes;
3018 :
3019 0 : mutex_lock(&port->mutex);
3020 0 : rxtrig_bytes = do_get_rxtrig(port);
3021 0 : mutex_unlock(&port->mutex);
3022 :
3023 0 : return rxtrig_bytes;
3024 : }
3025 :
3026 0 : static ssize_t rx_trig_bytes_show(struct device *dev,
3027 : struct device_attribute *attr, char *buf)
3028 : {
3029 0 : struct tty_port *port = dev_get_drvdata(dev);
3030 0 : int rxtrig_bytes;
3031 :
3032 0 : rxtrig_bytes = do_serial8250_get_rxtrig(port);
3033 0 : if (rxtrig_bytes < 0)
3034 0 : return rxtrig_bytes;
3035 :
3036 0 : return snprintf(buf, PAGE_SIZE, "%d\n", rxtrig_bytes);
3037 : }
3038 :
3039 0 : static int do_set_rxtrig(struct tty_port *port, unsigned char bytes)
3040 : {
3041 0 : struct uart_state *state = container_of(port, struct uart_state, port);
3042 0 : struct uart_port *uport = state->uart_port;
3043 0 : struct uart_8250_port *up = up_to_u8250p(uport);
3044 0 : int rxtrig;
3045 :
3046 0 : if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1 ||
3047 0 : up->fifo_bug)
3048 : return -EINVAL;
3049 :
3050 0 : rxtrig = bytes_to_fcr_rxtrig(up, bytes);
3051 0 : if (rxtrig < 0)
3052 : return rxtrig;
3053 :
3054 0 : serial8250_clear_fifos(up);
3055 0 : up->fcr &= ~UART_FCR_TRIGGER_MASK;
3056 0 : up->fcr |= (unsigned char)rxtrig;
3057 0 : serial_out(up, UART_FCR, up->fcr);
3058 0 : return 0;
3059 : }
3060 :
3061 0 : static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes)
3062 : {
3063 0 : int ret;
3064 :
3065 0 : mutex_lock(&port->mutex);
3066 0 : ret = do_set_rxtrig(port, bytes);
3067 0 : mutex_unlock(&port->mutex);
3068 :
3069 0 : return ret;
3070 : }
3071 :
3072 0 : static ssize_t rx_trig_bytes_store(struct device *dev,
3073 : struct device_attribute *attr, const char *buf, size_t count)
3074 : {
3075 0 : struct tty_port *port = dev_get_drvdata(dev);
3076 0 : unsigned char bytes;
3077 0 : int ret;
3078 :
3079 0 : if (!count)
3080 : return -EINVAL;
3081 :
3082 0 : ret = kstrtou8(buf, 10, &bytes);
3083 0 : if (ret < 0)
3084 0 : return ret;
3085 :
3086 0 : ret = do_serial8250_set_rxtrig(port, bytes);
3087 0 : if (ret < 0)
3088 0 : return ret;
3089 :
3090 0 : return count;
3091 : }
3092 :
3093 : static DEVICE_ATTR_RW(rx_trig_bytes);
3094 :
3095 : static struct attribute *serial8250_dev_attrs[] = {
3096 : &dev_attr_rx_trig_bytes.attr,
3097 : NULL
3098 : };
3099 :
3100 : static struct attribute_group serial8250_dev_attr_group = {
3101 : .attrs = serial8250_dev_attrs,
3102 : };
3103 :
3104 4 : static void register_dev_spec_attr_grp(struct uart_8250_port *up)
3105 : {
3106 4 : const struct serial8250_config *conf_type = &uart_config[up->port.type];
3107 :
3108 4 : if (conf_type->rxtrig_bytes[0])
3109 1 : up->port.attr_group = &serial8250_dev_attr_group;
3110 : }
3111 :
3112 4 : static void serial8250_config_port(struct uart_port *port, int flags)
3113 : {
3114 4 : struct uart_8250_port *up = up_to_u8250p(port);
3115 4 : int ret;
3116 :
3117 : /*
3118 : * Find the region that we can probe for. This in turn
3119 : * tells us whether we can probe for the type of port.
3120 : */
3121 4 : ret = serial8250_request_std_resource(up);
3122 4 : if (ret < 0)
3123 : return;
3124 :
3125 4 : if (port->iotype != up->cur_iotype)
3126 0 : set_io_from_upio(port);
3127 :
3128 4 : if (flags & UART_CONFIG_TYPE)
3129 4 : autoconfig(up);
3130 :
3131 4 : if (port->rs485.flags & SER_RS485_ENABLED)
3132 0 : port->rs485_config(port, &port->rs485);
3133 :
3134 : /* if access method is AU, it is a 16550 with a quirk */
3135 4 : if (port->type == PORT_16550A && port->iotype == UPIO_AU)
3136 0 : up->bugs |= UART_BUG_NOMSR;
3137 :
3138 : /* HW bugs may trigger IRQ while IIR == NO_INT */
3139 4 : if (port->type == PORT_TEGRA)
3140 0 : up->bugs |= UART_BUG_NOMSR;
3141 :
3142 4 : if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
3143 0 : autoconfig_irq(up);
3144 :
3145 4 : if (port->type == PORT_UNKNOWN)
3146 3 : serial8250_release_std_resource(up);
3147 :
3148 4 : register_dev_spec_attr_grp(up);
3149 4 : up->fcr = uart_config[up->port.type].fcr;
3150 : }
3151 :
3152 : static int
3153 0 : serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
3154 : {
3155 0 : if (ser->irq >= nr_irqs || ser->irq < 0 ||
3156 0 : ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
3157 0 : ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
3158 : ser->type == PORT_STARTECH)
3159 0 : return -EINVAL;
3160 : return 0;
3161 : }
3162 :
3163 1 : static const char *serial8250_type(struct uart_port *port)
3164 : {
3165 1 : int type = port->type;
3166 :
3167 1 : if (type >= ARRAY_SIZE(uart_config))
3168 0 : type = 0;
3169 1 : return uart_config[type].name;
3170 : }
3171 :
3172 : static const struct uart_ops serial8250_pops = {
3173 : .tx_empty = serial8250_tx_empty,
3174 : .set_mctrl = serial8250_set_mctrl,
3175 : .get_mctrl = serial8250_get_mctrl,
3176 : .stop_tx = serial8250_stop_tx,
3177 : .start_tx = serial8250_start_tx,
3178 : .throttle = serial8250_throttle,
3179 : .unthrottle = serial8250_unthrottle,
3180 : .stop_rx = serial8250_stop_rx,
3181 : .enable_ms = serial8250_enable_ms,
3182 : .break_ctl = serial8250_break_ctl,
3183 : .startup = serial8250_startup,
3184 : .shutdown = serial8250_shutdown,
3185 : .set_termios = serial8250_set_termios,
3186 : .set_ldisc = serial8250_set_ldisc,
3187 : .pm = serial8250_pm,
3188 : .type = serial8250_type,
3189 : .release_port = serial8250_release_port,
3190 : .request_port = serial8250_request_port,
3191 : .config_port = serial8250_config_port,
3192 : .verify_port = serial8250_verify_port,
3193 : #ifdef CONFIG_CONSOLE_POLL
3194 : .poll_get_char = serial8250_get_poll_char,
3195 : .poll_put_char = serial8250_put_poll_char,
3196 : #endif
3197 : };
3198 :
3199 4 : void serial8250_init_port(struct uart_8250_port *up)
3200 : {
3201 4 : struct uart_port *port = &up->port;
3202 :
3203 4 : spin_lock_init(&port->lock);
3204 4 : port->ops = &serial8250_pops;
3205 4 : port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE);
3206 :
3207 4 : up->cur_iotype = 0xFF;
3208 4 : }
3209 : EXPORT_SYMBOL_GPL(serial8250_init_port);
3210 :
3211 4 : void serial8250_set_defaults(struct uart_8250_port *up)
3212 : {
3213 4 : struct uart_port *port = &up->port;
3214 :
3215 4 : if (up->port.flags & UPF_FIXED_TYPE) {
3216 0 : unsigned int type = up->port.type;
3217 :
3218 0 : if (!up->port.fifosize)
3219 0 : up->port.fifosize = uart_config[type].fifo_size;
3220 0 : if (!up->tx_loadsz)
3221 0 : up->tx_loadsz = uart_config[type].tx_loadsz;
3222 0 : if (!up->capabilities)
3223 0 : up->capabilities = uart_config[type].flags;
3224 : }
3225 :
3226 4 : set_io_from_upio(port);
3227 :
3228 : /* default dma handlers */
3229 4 : if (up->dma) {
3230 0 : if (!up->dma->tx_dma)
3231 0 : up->dma->tx_dma = serial8250_tx_dma;
3232 0 : if (!up->dma->rx_dma)
3233 0 : up->dma->rx_dma = serial8250_rx_dma;
3234 : }
3235 4 : }
3236 : EXPORT_SYMBOL_GPL(serial8250_set_defaults);
3237 :
3238 : #ifdef CONFIG_SERIAL_8250_CONSOLE
3239 :
3240 13683 : static void serial8250_console_putchar(struct uart_port *port, int ch)
3241 : {
3242 13683 : struct uart_8250_port *up = up_to_u8250p(port);
3243 :
3244 13683 : wait_for_xmitr(up, UART_LSR_THRE);
3245 13683 : serial_port_out(port, UART_TX, ch);
3246 13683 : }
3247 :
3248 : /*
3249 : * Restore serial console when h/w power-off detected
3250 : */
3251 0 : static void serial8250_console_restore(struct uart_8250_port *up)
3252 : {
3253 0 : struct uart_port *port = &up->port;
3254 0 : struct ktermios termios;
3255 0 : unsigned int baud, quot, frac = 0;
3256 :
3257 0 : termios.c_cflag = port->cons->cflag;
3258 0 : if (port->state->port.tty && termios.c_cflag == 0)
3259 0 : termios.c_cflag = port->state->port.tty->termios.c_cflag;
3260 :
3261 0 : baud = serial8250_get_baud_rate(port, &termios, NULL);
3262 0 : quot = serial8250_get_divisor(port, baud, &frac);
3263 :
3264 0 : serial8250_set_divisor(port, baud, quot, frac);
3265 0 : serial_port_out(port, UART_LCR, up->lcr);
3266 0 : serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
3267 0 : }
3268 :
3269 : /*
3270 : * Print a string to the serial port trying not to disturb
3271 : * any possible real use of the port...
3272 : *
3273 : * The console_lock must be held when we get here.
3274 : *
3275 : * Doing runtime PM is really a bad idea for the kernel console.
3276 : * Thus, we assume the function is called when device is powered up.
3277 : */
3278 256 : void serial8250_console_write(struct uart_8250_port *up, const char *s,
3279 : unsigned int count)
3280 : {
3281 256 : struct uart_8250_em485 *em485 = up->em485;
3282 256 : struct uart_port *port = &up->port;
3283 256 : unsigned long flags;
3284 256 : unsigned int ier;
3285 256 : int locked = 1;
3286 :
3287 256 : touch_nmi_watchdog();
3288 :
3289 256 : if (oops_in_progress)
3290 0 : locked = spin_trylock_irqsave(&port->lock, flags);
3291 : else
3292 256 : spin_lock_irqsave(&port->lock, flags);
3293 :
3294 : /*
3295 : * First save the IER then disable the interrupts
3296 : */
3297 256 : ier = serial_port_in(port, UART_IER);
3298 :
3299 256 : if (up->capabilities & UART_CAP_UUE)
3300 0 : serial_port_out(port, UART_IER, UART_IER_UUE);
3301 : else
3302 256 : serial_port_out(port, UART_IER, 0);
3303 :
3304 : /* check scratch reg to see if port powered off during system sleep */
3305 256 : if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) {
3306 0 : serial8250_console_restore(up);
3307 0 : up->canary = 0;
3308 : }
3309 :
3310 256 : if (em485) {
3311 0 : if (em485->tx_stopped)
3312 0 : up->rs485_start_tx(up);
3313 0 : mdelay(port->rs485.delay_rts_before_send);
3314 : }
3315 :
3316 256 : uart_console_write(port, s, count, serial8250_console_putchar);
3317 :
3318 : /*
3319 : * Finally, wait for transmitter to become empty
3320 : * and restore the IER
3321 : */
3322 256 : wait_for_xmitr(up, BOTH_EMPTY);
3323 :
3324 256 : if (em485) {
3325 0 : mdelay(port->rs485.delay_rts_after_send);
3326 0 : if (em485->tx_stopped)
3327 0 : up->rs485_stop_tx(up);
3328 : }
3329 :
3330 256 : serial_port_out(port, UART_IER, ier);
3331 :
3332 : /*
3333 : * The receive handling will happen properly because the
3334 : * receive ready bit will still be set; it is not cleared
3335 : * on read. However, modem control will not, we must
3336 : * call it if we have saved something in the saved flags
3337 : * while processing with interrupts off.
3338 : */
3339 256 : if (up->msr_saved_flags)
3340 0 : serial8250_modem_status(up);
3341 :
3342 256 : if (locked)
3343 256 : spin_unlock_irqrestore(&port->lock, flags);
3344 256 : }
3345 :
3346 0 : static unsigned int probe_baud(struct uart_port *port)
3347 : {
3348 0 : unsigned char lcr, dll, dlm;
3349 0 : unsigned int quot;
3350 :
3351 0 : lcr = serial_port_in(port, UART_LCR);
3352 0 : serial_port_out(port, UART_LCR, lcr | UART_LCR_DLAB);
3353 0 : dll = serial_port_in(port, UART_DLL);
3354 0 : dlm = serial_port_in(port, UART_DLM);
3355 0 : serial_port_out(port, UART_LCR, lcr);
3356 :
3357 0 : quot = (dlm << 8) | dll;
3358 0 : return (port->uartclk / 16) / quot;
3359 : }
3360 :
3361 1 : int serial8250_console_setup(struct uart_port *port, char *options, bool probe)
3362 : {
3363 1 : int baud = 9600;
3364 1 : int bits = 8;
3365 1 : int parity = 'n';
3366 1 : int flow = 'n';
3367 1 : int ret;
3368 :
3369 1 : if (!port->iobase && !port->membase)
3370 : return -ENODEV;
3371 :
3372 1 : if (options)
3373 0 : uart_parse_options(options, &baud, &parity, &bits, &flow);
3374 1 : else if (probe)
3375 0 : baud = probe_baud(port);
3376 :
3377 1 : ret = uart_set_options(port, port->cons, baud, parity, bits, flow);
3378 1 : if (ret)
3379 0 : return ret;
3380 :
3381 : if (port->dev)
3382 1 : pm_runtime_get_sync(port->dev);
3383 :
3384 : return 0;
3385 : }
3386 :
3387 0 : int serial8250_console_exit(struct uart_port *port)
3388 : {
3389 0 : if (port->dev)
3390 0 : pm_runtime_put_sync(port->dev);
3391 :
3392 0 : return 0;
3393 : }
3394 :
3395 : #endif /* CONFIG_SERIAL_8250_CONSOLE */
3396 :
3397 : MODULE_LICENSE("GPL");
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