Line data Source code
1 : /* SPDX-License-Identifier: GPL-2.0 */
2 : /*
3 : * pci.h
4 : *
5 : * PCI defines and function prototypes
6 : * Copyright 1994, Drew Eckhardt
7 : * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
8 : *
9 : * PCI Express ASPM defines and function prototypes
10 : * Copyright (c) 2007 Intel Corp.
11 : * Zhang Yanmin (yanmin.zhang@intel.com)
12 : * Shaohua Li (shaohua.li@intel.com)
13 : *
14 : * For more information, please consult the following manuals (look at
15 : * http://www.pcisig.com/ for how to get them):
16 : *
17 : * PCI BIOS Specification
18 : * PCI Local Bus Specification
19 : * PCI to PCI Bridge Specification
20 : * PCI Express Specification
21 : * PCI System Design Guide
22 : */
23 : #ifndef LINUX_PCI_H
24 : #define LINUX_PCI_H
25 :
26 :
27 : #include <linux/mod_devicetable.h>
28 :
29 : #include <linux/types.h>
30 : #include <linux/init.h>
31 : #include <linux/ioport.h>
32 : #include <linux/list.h>
33 : #include <linux/compiler.h>
34 : #include <linux/errno.h>
35 : #include <linux/kobject.h>
36 : #include <linux/atomic.h>
37 : #include <linux/device.h>
38 : #include <linux/interrupt.h>
39 : #include <linux/io.h>
40 : #include <linux/resource_ext.h>
41 : #include <uapi/linux/pci.h>
42 :
43 : #include <linux/pci_ids.h>
44 :
45 : #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
46 : PCI_STATUS_SIG_SYSTEM_ERROR | \
47 : PCI_STATUS_REC_MASTER_ABORT | \
48 : PCI_STATUS_REC_TARGET_ABORT | \
49 : PCI_STATUS_SIG_TARGET_ABORT | \
50 : PCI_STATUS_PARITY)
51 :
52 : /*
53 : * The PCI interface treats multi-function devices as independent
54 : * devices. The slot/function address of each device is encoded
55 : * in a single byte as follows:
56 : *
57 : * 7:3 = slot
58 : * 2:0 = function
59 : *
60 : * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
61 : * In the interest of not exposing interfaces to user-space unnecessarily,
62 : * the following kernel-only defines are being added here.
63 : */
64 : #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
65 : /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
66 : #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
67 :
68 : /* pci_slot represents a physical slot */
69 : struct pci_slot {
70 : struct pci_bus *bus; /* Bus this slot is on */
71 : struct list_head list; /* Node in list of slots */
72 : struct hotplug_slot *hotplug; /* Hotplug info (move here) */
73 : unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
74 : struct kobject kobj;
75 : };
76 :
77 : static inline const char *pci_slot_name(const struct pci_slot *slot)
78 : {
79 : return kobject_name(&slot->kobj);
80 : }
81 :
82 : /* File state for mmap()s on /proc/bus/pci/X/Y */
83 : enum pci_mmap_state {
84 : pci_mmap_io,
85 : pci_mmap_mem
86 : };
87 :
88 : /* For PCI devices, the region numbers are assigned this way: */
89 : enum {
90 : /* #0-5: standard PCI resources */
91 : PCI_STD_RESOURCES,
92 : PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1,
93 :
94 : /* #6: expansion ROM resource */
95 : PCI_ROM_RESOURCE,
96 :
97 : /* Device-specific resources */
98 : #ifdef CONFIG_PCI_IOV
99 : PCI_IOV_RESOURCES,
100 : PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
101 : #endif
102 :
103 : /* PCI-to-PCI (P2P) bridge windows */
104 : #define PCI_BRIDGE_IO_WINDOW (PCI_BRIDGE_RESOURCES + 0)
105 : #define PCI_BRIDGE_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 1)
106 : #define PCI_BRIDGE_PREF_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 2)
107 :
108 : /* CardBus bridge windows */
109 : #define PCI_CB_BRIDGE_IO_0_WINDOW (PCI_BRIDGE_RESOURCES + 0)
110 : #define PCI_CB_BRIDGE_IO_1_WINDOW (PCI_BRIDGE_RESOURCES + 1)
111 : #define PCI_CB_BRIDGE_MEM_0_WINDOW (PCI_BRIDGE_RESOURCES + 2)
112 : #define PCI_CB_BRIDGE_MEM_1_WINDOW (PCI_BRIDGE_RESOURCES + 3)
113 :
114 : /* Total number of bridge resources for P2P and CardBus */
115 : #define PCI_BRIDGE_RESOURCE_NUM 4
116 :
117 : /* Resources assigned to buses behind the bridge */
118 : PCI_BRIDGE_RESOURCES,
119 : PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
120 : PCI_BRIDGE_RESOURCE_NUM - 1,
121 :
122 : /* Total resources associated with a PCI device */
123 : PCI_NUM_RESOURCES,
124 :
125 : /* Preserve this for compatibility */
126 : DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
127 : };
128 :
129 : /**
130 : * enum pci_interrupt_pin - PCI INTx interrupt values
131 : * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
132 : * @PCI_INTERRUPT_INTA: PCI INTA pin
133 : * @PCI_INTERRUPT_INTB: PCI INTB pin
134 : * @PCI_INTERRUPT_INTC: PCI INTC pin
135 : * @PCI_INTERRUPT_INTD: PCI INTD pin
136 : *
137 : * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
138 : * PCI_INTERRUPT_PIN register.
139 : */
140 : enum pci_interrupt_pin {
141 : PCI_INTERRUPT_UNKNOWN,
142 : PCI_INTERRUPT_INTA,
143 : PCI_INTERRUPT_INTB,
144 : PCI_INTERRUPT_INTC,
145 : PCI_INTERRUPT_INTD,
146 : };
147 :
148 : /* The number of legacy PCI INTx interrupts */
149 : #define PCI_NUM_INTX 4
150 :
151 : /*
152 : * pci_power_t values must match the bits in the Capabilities PME_Support
153 : * and Control/Status PowerState fields in the Power Management capability.
154 : */
155 : typedef int __bitwise pci_power_t;
156 :
157 : #define PCI_D0 ((pci_power_t __force) 0)
158 : #define PCI_D1 ((pci_power_t __force) 1)
159 : #define PCI_D2 ((pci_power_t __force) 2)
160 : #define PCI_D3hot ((pci_power_t __force) 3)
161 : #define PCI_D3cold ((pci_power_t __force) 4)
162 : #define PCI_UNKNOWN ((pci_power_t __force) 5)
163 : #define PCI_POWER_ERROR ((pci_power_t __force) -1)
164 :
165 : /* Remember to update this when the list above changes! */
166 : extern const char *pci_power_names[];
167 :
168 : static inline const char *pci_power_name(pci_power_t state)
169 : {
170 : return pci_power_names[1 + (__force int) state];
171 : }
172 :
173 : /**
174 : * typedef pci_channel_state_t
175 : *
176 : * The pci_channel state describes connectivity between the CPU and
177 : * the PCI device. If some PCI bus between here and the PCI device
178 : * has crashed or locked up, this info is reflected here.
179 : */
180 : typedef unsigned int __bitwise pci_channel_state_t;
181 :
182 : enum {
183 : /* I/O channel is in normal state */
184 : pci_channel_io_normal = (__force pci_channel_state_t) 1,
185 :
186 : /* I/O to channel is blocked */
187 : pci_channel_io_frozen = (__force pci_channel_state_t) 2,
188 :
189 : /* PCI card is dead */
190 : pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
191 : };
192 :
193 : typedef unsigned int __bitwise pcie_reset_state_t;
194 :
195 : enum pcie_reset_state {
196 : /* Reset is NOT asserted (Use to deassert reset) */
197 : pcie_deassert_reset = (__force pcie_reset_state_t) 1,
198 :
199 : /* Use #PERST to reset PCIe device */
200 : pcie_warm_reset = (__force pcie_reset_state_t) 2,
201 :
202 : /* Use PCIe Hot Reset to reset device */
203 : pcie_hot_reset = (__force pcie_reset_state_t) 3
204 : };
205 :
206 : typedef unsigned short __bitwise pci_dev_flags_t;
207 : enum pci_dev_flags {
208 : /* INTX_DISABLE in PCI_COMMAND register disables MSI too */
209 : PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
210 : /* Device configuration is irrevocably lost if disabled into D3 */
211 : PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
212 : /* Provide indication device is assigned by a Virtual Machine Manager */
213 : PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
214 : /* Flag for quirk use to store if quirk-specific ACS is enabled */
215 : PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
216 : /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
217 : PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
218 : /* Do not use bus resets for device */
219 : PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
220 : /* Do not use PM reset even if device advertises NoSoftRst- */
221 : PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
222 : /* Get VPD from function 0 VPD */
223 : PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
224 : /* A non-root bridge where translation occurs, stop alias search here */
225 : PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
226 : /* Do not use FLR even if device advertises PCI_AF_CAP */
227 : PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
228 : /* Don't use Relaxed Ordering for TLPs directed at this device */
229 : PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
230 : };
231 :
232 : enum pci_irq_reroute_variant {
233 : INTEL_IRQ_REROUTE_VARIANT = 1,
234 : MAX_IRQ_REROUTE_VARIANTS = 3
235 : };
236 :
237 : typedef unsigned short __bitwise pci_bus_flags_t;
238 : enum pci_bus_flags {
239 : PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
240 : PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
241 : PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
242 : PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8,
243 : };
244 :
245 : /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
246 : enum pcie_link_width {
247 : PCIE_LNK_WIDTH_RESRV = 0x00,
248 : PCIE_LNK_X1 = 0x01,
249 : PCIE_LNK_X2 = 0x02,
250 : PCIE_LNK_X4 = 0x04,
251 : PCIE_LNK_X8 = 0x08,
252 : PCIE_LNK_X12 = 0x0c,
253 : PCIE_LNK_X16 = 0x10,
254 : PCIE_LNK_X32 = 0x20,
255 : PCIE_LNK_WIDTH_UNKNOWN = 0xff,
256 : };
257 :
258 : /* See matching string table in pci_speed_string() */
259 : enum pci_bus_speed {
260 : PCI_SPEED_33MHz = 0x00,
261 : PCI_SPEED_66MHz = 0x01,
262 : PCI_SPEED_66MHz_PCIX = 0x02,
263 : PCI_SPEED_100MHz_PCIX = 0x03,
264 : PCI_SPEED_133MHz_PCIX = 0x04,
265 : PCI_SPEED_66MHz_PCIX_ECC = 0x05,
266 : PCI_SPEED_100MHz_PCIX_ECC = 0x06,
267 : PCI_SPEED_133MHz_PCIX_ECC = 0x07,
268 : PCI_SPEED_66MHz_PCIX_266 = 0x09,
269 : PCI_SPEED_100MHz_PCIX_266 = 0x0a,
270 : PCI_SPEED_133MHz_PCIX_266 = 0x0b,
271 : AGP_UNKNOWN = 0x0c,
272 : AGP_1X = 0x0d,
273 : AGP_2X = 0x0e,
274 : AGP_4X = 0x0f,
275 : AGP_8X = 0x10,
276 : PCI_SPEED_66MHz_PCIX_533 = 0x11,
277 : PCI_SPEED_100MHz_PCIX_533 = 0x12,
278 : PCI_SPEED_133MHz_PCIX_533 = 0x13,
279 : PCIE_SPEED_2_5GT = 0x14,
280 : PCIE_SPEED_5_0GT = 0x15,
281 : PCIE_SPEED_8_0GT = 0x16,
282 : PCIE_SPEED_16_0GT = 0x17,
283 : PCIE_SPEED_32_0GT = 0x18,
284 : PCIE_SPEED_64_0GT = 0x19,
285 : PCI_SPEED_UNKNOWN = 0xff,
286 : };
287 :
288 : enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
289 : enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
290 :
291 : struct pci_cap_saved_data {
292 : u16 cap_nr;
293 : bool cap_extended;
294 : unsigned int size;
295 : u32 data[];
296 : };
297 :
298 : struct pci_cap_saved_state {
299 : struct hlist_node next;
300 : struct pci_cap_saved_data cap;
301 : };
302 :
303 : struct irq_affinity;
304 : struct pcie_link_state;
305 : struct pci_vpd;
306 : struct pci_sriov;
307 : struct pci_p2pdma;
308 : struct rcec_ea;
309 :
310 : /* The pci_dev structure describes PCI devices */
311 : struct pci_dev {
312 : struct list_head bus_list; /* Node in per-bus list */
313 : struct pci_bus *bus; /* Bus this device is on */
314 : struct pci_bus *subordinate; /* Bus this device bridges to */
315 :
316 : void *sysdata; /* Hook for sys-specific extension */
317 : struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */
318 : struct pci_slot *slot; /* Physical slot this device is in */
319 :
320 : unsigned int devfn; /* Encoded device & function index */
321 : unsigned short vendor;
322 : unsigned short device;
323 : unsigned short subsystem_vendor;
324 : unsigned short subsystem_device;
325 : unsigned int class; /* 3 bytes: (base,sub,prog-if) */
326 : u8 revision; /* PCI revision, low byte of class word */
327 : u8 hdr_type; /* PCI header type (`multi' flag masked out) */
328 : #ifdef CONFIG_PCIEAER
329 : u16 aer_cap; /* AER capability offset */
330 : struct aer_stats *aer_stats; /* AER stats for this device */
331 : #endif
332 : #ifdef CONFIG_PCIEPORTBUS
333 : struct rcec_ea *rcec_ea; /* RCEC cached endpoint association */
334 : struct pci_dev *rcec; /* Associated RCEC device */
335 : #endif
336 : u8 pcie_cap; /* PCIe capability offset */
337 : u8 msi_cap; /* MSI capability offset */
338 : u8 msix_cap; /* MSI-X capability offset */
339 : u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
340 : u8 rom_base_reg; /* Config register controlling ROM */
341 : u8 pin; /* Interrupt pin this device uses */
342 : u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */
343 : unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
344 :
345 : struct pci_driver *driver; /* Driver bound to this device */
346 : u64 dma_mask; /* Mask of the bits of bus address this
347 : device implements. Normally this is
348 : 0xffffffff. You only need to change
349 : this if your device has broken DMA
350 : or supports 64-bit transfers. */
351 :
352 : struct device_dma_parameters dma_parms;
353 :
354 : pci_power_t current_state; /* Current operating state. In ACPI,
355 : this is D0-D3, D0 being fully
356 : functional, and D3 being off. */
357 : unsigned int imm_ready:1; /* Supports Immediate Readiness */
358 : u8 pm_cap; /* PM capability offset */
359 : unsigned int pme_support:5; /* Bitmask of states from which PME#
360 : can be generated */
361 : unsigned int pme_poll:1; /* Poll device's PME status bit */
362 : unsigned int d1_support:1; /* Low power state D1 is supported */
363 : unsigned int d2_support:1; /* Low power state D2 is supported */
364 : unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
365 : unsigned int no_d3cold:1; /* D3cold is forbidden */
366 : unsigned int bridge_d3:1; /* Allow D3 for bridge */
367 : unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
368 : unsigned int mmio_always_on:1; /* Disallow turning off io/mem
369 : decoding during BAR sizing */
370 : unsigned int wakeup_prepared:1;
371 : unsigned int runtime_d3cold:1; /* Whether go through runtime
372 : D3cold, not set for devices
373 : powered on/off by the
374 : corresponding bridge */
375 : unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */
376 : unsigned int ignore_hotplug:1; /* Ignore hotplug events */
377 : unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
378 : controlled exclusively by
379 : user sysfs */
380 : unsigned int clear_retrain_link:1; /* Need to clear Retrain Link
381 : bit manually */
382 : unsigned int d3hot_delay; /* D3hot->D0 transition time in ms */
383 : unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
384 :
385 : #ifdef CONFIG_PCIEASPM
386 : struct pcie_link_state *link_state; /* ASPM link state */
387 : unsigned int ltr_path:1; /* Latency Tolerance Reporting
388 : supported from root to here */
389 : u16 l1ss; /* L1SS Capability pointer */
390 : #endif
391 : unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */
392 :
393 : pci_channel_state_t error_state; /* Current connectivity state */
394 : struct device dev; /* Generic device interface */
395 :
396 : int cfg_size; /* Size of config space */
397 :
398 : /*
399 : * Instead of touching interrupt line and base address registers
400 : * directly, use the values stored here. They might be different!
401 : */
402 : unsigned int irq;
403 : struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
404 :
405 : bool match_driver; /* Skip attaching driver */
406 :
407 : unsigned int transparent:1; /* Subtractive decode bridge */
408 : unsigned int io_window:1; /* Bridge has I/O window */
409 : unsigned int pref_window:1; /* Bridge has pref mem window */
410 : unsigned int pref_64_window:1; /* Pref mem window is 64-bit */
411 : unsigned int multifunction:1; /* Multi-function device */
412 :
413 : unsigned int is_busmaster:1; /* Is busmaster */
414 : unsigned int no_msi:1; /* May not use MSI */
415 : unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */
416 : unsigned int block_cfg_access:1; /* Config space access blocked */
417 : unsigned int broken_parity_status:1; /* Generates false positive parity */
418 : unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */
419 : unsigned int msi_enabled:1;
420 : unsigned int msix_enabled:1;
421 : unsigned int ari_enabled:1; /* ARI forwarding */
422 : unsigned int ats_enabled:1; /* Address Translation Svc */
423 : unsigned int pasid_enabled:1; /* Process Address Space ID */
424 : unsigned int pri_enabled:1; /* Page Request Interface */
425 : unsigned int is_managed:1;
426 : unsigned int needs_freset:1; /* Requires fundamental reset */
427 : unsigned int state_saved:1;
428 : unsigned int is_physfn:1;
429 : unsigned int is_virtfn:1;
430 : unsigned int reset_fn:1;
431 : unsigned int is_hotplug_bridge:1;
432 : unsigned int shpc_managed:1; /* SHPC owned by shpchp */
433 : unsigned int is_thunderbolt:1; /* Thunderbolt controller */
434 : /*
435 : * Devices marked being untrusted are the ones that can potentially
436 : * execute DMA attacks and similar. They are typically connected
437 : * through external ports such as Thunderbolt but not limited to
438 : * that. When an IOMMU is enabled they should be getting full
439 : * mappings to make sure they cannot access arbitrary memory.
440 : */
441 : unsigned int untrusted:1;
442 : /*
443 : * Info from the platform, e.g., ACPI or device tree, may mark a
444 : * device as "external-facing". An external-facing device is
445 : * itself internal but devices downstream from it are external.
446 : */
447 : unsigned int external_facing:1;
448 : unsigned int broken_intx_masking:1; /* INTx masking can't be used */
449 : unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */
450 : unsigned int irq_managed:1;
451 : unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */
452 : unsigned int is_probed:1; /* Device probing in progress */
453 : unsigned int link_active_reporting:1;/* Device capable of reporting link active */
454 : unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */
455 : unsigned int no_command_memory:1; /* No PCI_COMMAND_MEMORY */
456 : pci_dev_flags_t dev_flags;
457 : atomic_t enable_cnt; /* pci_enable_device has been called */
458 :
459 : u32 saved_config_space[16]; /* Config space saved at suspend time */
460 : struct hlist_head saved_cap_space;
461 : struct bin_attribute *rom_attr; /* Attribute descriptor for sysfs ROM entry */
462 : int rom_attr_enabled; /* Display of ROM attribute enabled? */
463 : struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
464 : struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
465 :
466 : #ifdef CONFIG_HOTPLUG_PCI_PCIE
467 : unsigned int broken_cmd_compl:1; /* No compl for some cmds */
468 : #endif
469 : #ifdef CONFIG_PCIE_PTM
470 : unsigned int ptm_root:1;
471 : unsigned int ptm_enabled:1;
472 : u8 ptm_granularity;
473 : #endif
474 : #ifdef CONFIG_PCI_MSI
475 : const struct attribute_group **msi_irq_groups;
476 : #endif
477 : struct pci_vpd *vpd;
478 : #ifdef CONFIG_PCIE_DPC
479 : u16 dpc_cap;
480 : unsigned int dpc_rp_extensions:1;
481 : u8 dpc_rp_log_size;
482 : #endif
483 : #ifdef CONFIG_PCI_ATS
484 : union {
485 : struct pci_sriov *sriov; /* PF: SR-IOV info */
486 : struct pci_dev *physfn; /* VF: related PF */
487 : };
488 : u16 ats_cap; /* ATS Capability offset */
489 : u8 ats_stu; /* ATS Smallest Translation Unit */
490 : #endif
491 : #ifdef CONFIG_PCI_PRI
492 : u16 pri_cap; /* PRI Capability offset */
493 : u32 pri_reqs_alloc; /* Number of PRI requests allocated */
494 : unsigned int pasid_required:1; /* PRG Response PASID Required */
495 : #endif
496 : #ifdef CONFIG_PCI_PASID
497 : u16 pasid_cap; /* PASID Capability offset */
498 : u16 pasid_features;
499 : #endif
500 : #ifdef CONFIG_PCI_P2PDMA
501 : struct pci_p2pdma *p2pdma;
502 : #endif
503 : u16 acs_cap; /* ACS Capability offset */
504 : phys_addr_t rom; /* Physical address if not from BAR */
505 : size_t romlen; /* Length if not from BAR */
506 : char *driver_override; /* Driver name to force a match */
507 :
508 : unsigned long priv_flags; /* Private flags for the PCI driver */
509 : };
510 :
511 : static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
512 : {
513 : #ifdef CONFIG_PCI_IOV
514 : if (dev->is_virtfn)
515 : dev = dev->physfn;
516 : #endif
517 : return dev;
518 : }
519 :
520 : struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
521 :
522 : #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
523 : #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
524 :
525 : static inline int pci_channel_offline(struct pci_dev *pdev)
526 : {
527 : return (pdev->error_state != pci_channel_io_normal);
528 : }
529 :
530 : struct pci_host_bridge {
531 : struct device dev;
532 : struct pci_bus *bus; /* Root bus */
533 : struct pci_ops *ops;
534 : struct pci_ops *child_ops;
535 : void *sysdata;
536 : int busnr;
537 : struct list_head windows; /* resource_entry */
538 : struct list_head dma_ranges; /* dma ranges resource list */
539 : u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */
540 : int (*map_irq)(const struct pci_dev *, u8, u8);
541 : void (*release_fn)(struct pci_host_bridge *);
542 : void *release_data;
543 : struct msi_controller *msi;
544 : unsigned int ignore_reset_delay:1; /* For entire hierarchy */
545 : unsigned int no_ext_tags:1; /* No Extended Tags */
546 : unsigned int native_aer:1; /* OS may use PCIe AER */
547 : unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */
548 : unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */
549 : unsigned int native_pme:1; /* OS may use PCIe PME */
550 : unsigned int native_ltr:1; /* OS may use PCIe LTR */
551 : unsigned int native_dpc:1; /* OS may use PCIe DPC */
552 : unsigned int preserve_config:1; /* Preserve FW resource setup */
553 : unsigned int size_windows:1; /* Enable root bus sizing */
554 :
555 : /* Resource alignment requirements */
556 : resource_size_t (*align_resource)(struct pci_dev *dev,
557 : const struct resource *res,
558 : resource_size_t start,
559 : resource_size_t size,
560 : resource_size_t align);
561 : unsigned long private[] ____cacheline_aligned;
562 : };
563 :
564 : #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
565 :
566 : static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
567 : {
568 : return (void *)bridge->private;
569 : }
570 :
571 : static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
572 : {
573 : return container_of(priv, struct pci_host_bridge, private);
574 : }
575 :
576 : struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
577 : struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
578 : size_t priv);
579 : void pci_free_host_bridge(struct pci_host_bridge *bridge);
580 : struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
581 :
582 : void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
583 : void (*release_fn)(struct pci_host_bridge *),
584 : void *release_data);
585 :
586 : int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
587 :
588 : /*
589 : * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
590 : * to P2P or CardBus bridge windows) go in a table. Additional ones (for
591 : * buses below host bridges or subtractive decode bridges) go in the list.
592 : * Use pci_bus_for_each_resource() to iterate through all the resources.
593 : */
594 :
595 : /*
596 : * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
597 : * and there's no way to program the bridge with the details of the window.
598 : * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
599 : * decode bit set, because they are explicit and can be programmed with _SRS.
600 : */
601 : #define PCI_SUBTRACTIVE_DECODE 0x1
602 :
603 : struct pci_bus_resource {
604 : struct list_head list;
605 : struct resource *res;
606 : unsigned int flags;
607 : };
608 :
609 : #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
610 :
611 : struct pci_bus {
612 : struct list_head node; /* Node in list of buses */
613 : struct pci_bus *parent; /* Parent bus this bridge is on */
614 : struct list_head children; /* List of child buses */
615 : struct list_head devices; /* List of devices on this bus */
616 : struct pci_dev *self; /* Bridge device as seen by parent */
617 : struct list_head slots; /* List of slots on this bus;
618 : protected by pci_slot_mutex */
619 : struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
620 : struct list_head resources; /* Address space routed to this bus */
621 : struct resource busn_res; /* Bus numbers routed to this bus */
622 :
623 : struct pci_ops *ops; /* Configuration access functions */
624 : struct msi_controller *msi; /* MSI controller */
625 : void *sysdata; /* Hook for sys-specific extension */
626 : struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */
627 :
628 : unsigned char number; /* Bus number */
629 : unsigned char primary; /* Number of primary bridge */
630 : unsigned char max_bus_speed; /* enum pci_bus_speed */
631 : unsigned char cur_bus_speed; /* enum pci_bus_speed */
632 : #ifdef CONFIG_PCI_DOMAINS_GENERIC
633 : int domain_nr;
634 : #endif
635 :
636 : char name[48];
637 :
638 : unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */
639 : pci_bus_flags_t bus_flags; /* Inherited by child buses */
640 : struct device *bridge;
641 : struct device dev;
642 : struct bin_attribute *legacy_io; /* Legacy I/O for this bus */
643 : struct bin_attribute *legacy_mem; /* Legacy mem */
644 : unsigned int is_added:1;
645 : };
646 :
647 : #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
648 :
649 : static inline u16 pci_dev_id(struct pci_dev *dev)
650 : {
651 : return PCI_DEVID(dev->bus->number, dev->devfn);
652 : }
653 :
654 : /*
655 : * Returns true if the PCI bus is root (behind host-PCI bridge),
656 : * false otherwise
657 : *
658 : * Some code assumes that "bus->self == NULL" means that bus is a root bus.
659 : * This is incorrect because "virtual" buses added for SR-IOV (via
660 : * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
661 : */
662 : static inline bool pci_is_root_bus(struct pci_bus *pbus)
663 : {
664 : return !(pbus->parent);
665 : }
666 :
667 : /**
668 : * pci_is_bridge - check if the PCI device is a bridge
669 : * @dev: PCI device
670 : *
671 : * Return true if the PCI device is bridge whether it has subordinate
672 : * or not.
673 : */
674 : static inline bool pci_is_bridge(struct pci_dev *dev)
675 : {
676 : return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
677 : dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
678 : }
679 :
680 : #define for_each_pci_bridge(dev, bus) \
681 : list_for_each_entry(dev, &bus->devices, bus_list) \
682 : if (!pci_is_bridge(dev)) {} else
683 :
684 : static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
685 : {
686 : dev = pci_physfn(dev);
687 : if (pci_is_root_bus(dev->bus))
688 : return NULL;
689 :
690 : return dev->bus->self;
691 : }
692 :
693 : #ifdef CONFIG_PCI_MSI
694 : static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
695 : {
696 : return pci_dev->msi_enabled || pci_dev->msix_enabled;
697 : }
698 : #else
699 : static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
700 : #endif
701 :
702 : /* Error values that may be returned by PCI functions */
703 : #define PCIBIOS_SUCCESSFUL 0x00
704 : #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
705 : #define PCIBIOS_BAD_VENDOR_ID 0x83
706 : #define PCIBIOS_DEVICE_NOT_FOUND 0x86
707 : #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
708 : #define PCIBIOS_SET_FAILED 0x88
709 : #define PCIBIOS_BUFFER_TOO_SMALL 0x89
710 :
711 : /* Translate above to generic errno for passing back through non-PCI code */
712 : static inline int pcibios_err_to_errno(int err)
713 : {
714 : if (err <= PCIBIOS_SUCCESSFUL)
715 : return err; /* Assume already errno */
716 :
717 : switch (err) {
718 : case PCIBIOS_FUNC_NOT_SUPPORTED:
719 : return -ENOENT;
720 : case PCIBIOS_BAD_VENDOR_ID:
721 : return -ENOTTY;
722 : case PCIBIOS_DEVICE_NOT_FOUND:
723 : return -ENODEV;
724 : case PCIBIOS_BAD_REGISTER_NUMBER:
725 : return -EFAULT;
726 : case PCIBIOS_SET_FAILED:
727 : return -EIO;
728 : case PCIBIOS_BUFFER_TOO_SMALL:
729 : return -ENOSPC;
730 : }
731 :
732 : return -ERANGE;
733 : }
734 :
735 : /* Low-level architecture-dependent routines */
736 :
737 : struct pci_ops {
738 : int (*add_bus)(struct pci_bus *bus);
739 : void (*remove_bus)(struct pci_bus *bus);
740 : void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
741 : int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
742 : int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
743 : };
744 :
745 : /*
746 : * ACPI needs to be able to access PCI config space before we've done a
747 : * PCI bus scan and created pci_bus structures.
748 : */
749 : int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
750 : int reg, int len, u32 *val);
751 : int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
752 : int reg, int len, u32 val);
753 :
754 : #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
755 : typedef u64 pci_bus_addr_t;
756 : #else
757 : typedef u32 pci_bus_addr_t;
758 : #endif
759 :
760 : struct pci_bus_region {
761 : pci_bus_addr_t start;
762 : pci_bus_addr_t end;
763 : };
764 :
765 : struct pci_dynids {
766 : spinlock_t lock; /* Protects list, index */
767 : struct list_head list; /* For IDs added at runtime */
768 : };
769 :
770 :
771 : /*
772 : * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
773 : * a set of callbacks in struct pci_error_handlers, that device driver
774 : * will be notified of PCI bus errors, and will be driven to recovery
775 : * when an error occurs.
776 : */
777 :
778 : typedef unsigned int __bitwise pci_ers_result_t;
779 :
780 : enum pci_ers_result {
781 : /* No result/none/not supported in device driver */
782 : PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
783 :
784 : /* Device driver can recover without slot reset */
785 : PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
786 :
787 : /* Device driver wants slot to be reset */
788 : PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
789 :
790 : /* Device has completely failed, is unrecoverable */
791 : PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
792 :
793 : /* Device driver is fully recovered and operational */
794 : PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
795 :
796 : /* No AER capabilities registered for the driver */
797 : PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
798 : };
799 :
800 : /* PCI bus error event callbacks */
801 : struct pci_error_handlers {
802 : /* PCI bus error detected on this device */
803 : pci_ers_result_t (*error_detected)(struct pci_dev *dev,
804 : pci_channel_state_t error);
805 :
806 : /* MMIO has been re-enabled, but not DMA */
807 : pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
808 :
809 : /* PCI slot has been reset */
810 : pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
811 :
812 : /* PCI function reset prepare or completed */
813 : void (*reset_prepare)(struct pci_dev *dev);
814 : void (*reset_done)(struct pci_dev *dev);
815 :
816 : /* Device driver may resume normal operations */
817 : void (*resume)(struct pci_dev *dev);
818 : };
819 :
820 :
821 : struct module;
822 :
823 : /**
824 : * struct pci_driver - PCI driver structure
825 : * @node: List of driver structures.
826 : * @name: Driver name.
827 : * @id_table: Pointer to table of device IDs the driver is
828 : * interested in. Most drivers should export this
829 : * table using MODULE_DEVICE_TABLE(pci,...).
830 : * @probe: This probing function gets called (during execution
831 : * of pci_register_driver() for already existing
832 : * devices or later if a new device gets inserted) for
833 : * all PCI devices which match the ID table and are not
834 : * "owned" by the other drivers yet. This function gets
835 : * passed a "struct pci_dev \*" for each device whose
836 : * entry in the ID table matches the device. The probe
837 : * function returns zero when the driver chooses to
838 : * take "ownership" of the device or an error code
839 : * (negative number) otherwise.
840 : * The probe function always gets called from process
841 : * context, so it can sleep.
842 : * @remove: The remove() function gets called whenever a device
843 : * being handled by this driver is removed (either during
844 : * deregistration of the driver or when it's manually
845 : * pulled out of a hot-pluggable slot).
846 : * The remove function always gets called from process
847 : * context, so it can sleep.
848 : * @suspend: Put device into low power state.
849 : * @resume: Wake device from low power state.
850 : * (Please see Documentation/power/pci.rst for descriptions
851 : * of PCI Power Management and the related functions.)
852 : * @shutdown: Hook into reboot_notifier_list (kernel/sys.c).
853 : * Intended to stop any idling DMA operations.
854 : * Useful for enabling wake-on-lan (NIC) or changing
855 : * the power state of a device before reboot.
856 : * e.g. drivers/net/e100.c.
857 : * @sriov_configure: Optional driver callback to allow configuration of
858 : * number of VFs to enable via sysfs "sriov_numvfs" file.
859 : * @err_handler: See Documentation/PCI/pci-error-recovery.rst
860 : * @groups: Sysfs attribute groups.
861 : * @driver: Driver model structure.
862 : * @dynids: List of dynamically added device IDs.
863 : */
864 : struct pci_driver {
865 : struct list_head node;
866 : const char *name;
867 : const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */
868 : int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
869 : void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
870 : int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */
871 : int (*resume)(struct pci_dev *dev); /* Device woken up */
872 : void (*shutdown)(struct pci_dev *dev);
873 : int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */
874 : const struct pci_error_handlers *err_handler;
875 : const struct attribute_group **groups;
876 : struct device_driver driver;
877 : struct pci_dynids dynids;
878 : };
879 :
880 : #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
881 :
882 : /**
883 : * PCI_DEVICE - macro used to describe a specific PCI device
884 : * @vend: the 16 bit PCI Vendor ID
885 : * @dev: the 16 bit PCI Device ID
886 : *
887 : * This macro is used to create a struct pci_device_id that matches a
888 : * specific device. The subvendor and subdevice fields will be set to
889 : * PCI_ANY_ID.
890 : */
891 : #define PCI_DEVICE(vend,dev) \
892 : .vendor = (vend), .device = (dev), \
893 : .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
894 :
895 : /**
896 : * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem
897 : * @vend: the 16 bit PCI Vendor ID
898 : * @dev: the 16 bit PCI Device ID
899 : * @subvend: the 16 bit PCI Subvendor ID
900 : * @subdev: the 16 bit PCI Subdevice ID
901 : *
902 : * This macro is used to create a struct pci_device_id that matches a
903 : * specific device with subsystem information.
904 : */
905 : #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
906 : .vendor = (vend), .device = (dev), \
907 : .subvendor = (subvend), .subdevice = (subdev)
908 :
909 : /**
910 : * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class
911 : * @dev_class: the class, subclass, prog-if triple for this device
912 : * @dev_class_mask: the class mask for this device
913 : *
914 : * This macro is used to create a struct pci_device_id that matches a
915 : * specific PCI class. The vendor, device, subvendor, and subdevice
916 : * fields will be set to PCI_ANY_ID.
917 : */
918 : #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
919 : .class = (dev_class), .class_mask = (dev_class_mask), \
920 : .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
921 : .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
922 :
923 : /**
924 : * PCI_VDEVICE - macro used to describe a specific PCI device in short form
925 : * @vend: the vendor name
926 : * @dev: the 16 bit PCI Device ID
927 : *
928 : * This macro is used to create a struct pci_device_id that matches a
929 : * specific PCI device. The subvendor, and subdevice fields will be set
930 : * to PCI_ANY_ID. The macro allows the next field to follow as the device
931 : * private data.
932 : */
933 : #define PCI_VDEVICE(vend, dev) \
934 : .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
935 : .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
936 :
937 : /**
938 : * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form
939 : * @vend: the vendor name (without PCI_VENDOR_ID_ prefix)
940 : * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix)
941 : * @data: the driver data to be filled
942 : *
943 : * This macro is used to create a struct pci_device_id that matches a
944 : * specific PCI device. The subvendor, and subdevice fields will be set
945 : * to PCI_ANY_ID.
946 : */
947 : #define PCI_DEVICE_DATA(vend, dev, data) \
948 : .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \
949 : .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \
950 : .driver_data = (kernel_ulong_t)(data)
951 :
952 : enum {
953 : PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */
954 : PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */
955 : PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */
956 : PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */
957 : PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */
958 : PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
959 : PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */
960 : };
961 :
962 : #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */
963 : #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */
964 : #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */
965 : #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */
966 :
967 : /* These external functions are only available when PCI support is enabled */
968 : #ifdef CONFIG_PCI
969 :
970 : extern unsigned int pci_flags;
971 :
972 : static inline void pci_set_flags(int flags) { pci_flags = flags; }
973 : static inline void pci_add_flags(int flags) { pci_flags |= flags; }
974 : static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
975 : static inline int pci_has_flag(int flag) { return pci_flags & flag; }
976 :
977 : void pcie_bus_configure_settings(struct pci_bus *bus);
978 :
979 : enum pcie_bus_config_types {
980 : PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */
981 : PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */
982 : PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */
983 : PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */
984 : PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */
985 : };
986 :
987 : extern enum pcie_bus_config_types pcie_bus_config;
988 :
989 : extern struct bus_type pci_bus_type;
990 :
991 : /* Do NOT directly access these two variables, unless you are arch-specific PCI
992 : * code, or PCI core code. */
993 : extern struct list_head pci_root_buses; /* List of all known PCI buses */
994 : /* Some device drivers need know if PCI is initiated */
995 : int no_pci_devices(void);
996 :
997 : void pcibios_resource_survey_bus(struct pci_bus *bus);
998 : void pcibios_bus_add_device(struct pci_dev *pdev);
999 : void pcibios_add_bus(struct pci_bus *bus);
1000 : void pcibios_remove_bus(struct pci_bus *bus);
1001 : void pcibios_fixup_bus(struct pci_bus *);
1002 : int __must_check pcibios_enable_device(struct pci_dev *, int mask);
1003 : /* Architecture-specific versions may override this (weak) */
1004 : char *pcibios_setup(char *str);
1005 :
1006 : /* Used only when drivers/pci/setup.c is used */
1007 : resource_size_t pcibios_align_resource(void *, const struct resource *,
1008 : resource_size_t,
1009 : resource_size_t);
1010 :
1011 : /* Weak but can be overridden by arch */
1012 : void pci_fixup_cardbus(struct pci_bus *);
1013 :
1014 : /* Generic PCI functions used internally */
1015 :
1016 : void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
1017 : struct resource *res);
1018 : void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
1019 : struct pci_bus_region *region);
1020 : void pcibios_scan_specific_bus(int busn);
1021 : struct pci_bus *pci_find_bus(int domain, int busnr);
1022 : void pci_bus_add_devices(const struct pci_bus *bus);
1023 : struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
1024 : struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
1025 : struct pci_ops *ops, void *sysdata,
1026 : struct list_head *resources);
1027 : int pci_host_probe(struct pci_host_bridge *bridge);
1028 : int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
1029 : int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
1030 : void pci_bus_release_busn_res(struct pci_bus *b);
1031 : struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
1032 : struct pci_ops *ops, void *sysdata,
1033 : struct list_head *resources);
1034 : int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
1035 : struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
1036 : int busnr);
1037 : struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
1038 : const char *name,
1039 : struct hotplug_slot *hotplug);
1040 : void pci_destroy_slot(struct pci_slot *slot);
1041 : #ifdef CONFIG_SYSFS
1042 : void pci_dev_assign_slot(struct pci_dev *dev);
1043 : #else
1044 : static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
1045 : #endif
1046 : int pci_scan_slot(struct pci_bus *bus, int devfn);
1047 : struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
1048 : void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1049 : unsigned int pci_scan_child_bus(struct pci_bus *bus);
1050 : void pci_bus_add_device(struct pci_dev *dev);
1051 : void pci_read_bridge_bases(struct pci_bus *child);
1052 : struct resource *pci_find_parent_resource(const struct pci_dev *dev,
1053 : struct resource *res);
1054 : u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
1055 : int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
1056 : u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
1057 : struct pci_dev *pci_dev_get(struct pci_dev *dev);
1058 : void pci_dev_put(struct pci_dev *dev);
1059 : void pci_remove_bus(struct pci_bus *b);
1060 : void pci_stop_and_remove_bus_device(struct pci_dev *dev);
1061 : void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
1062 : void pci_stop_root_bus(struct pci_bus *bus);
1063 : void pci_remove_root_bus(struct pci_bus *bus);
1064 : void pci_setup_cardbus(struct pci_bus *bus);
1065 : void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
1066 : void pci_sort_breadthfirst(void);
1067 : #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
1068 : #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
1069 :
1070 : /* Generic PCI functions exported to card drivers */
1071 :
1072 : u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1073 : u8 pci_find_capability(struct pci_dev *dev, int cap);
1074 : u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
1075 : u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
1076 : u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap);
1077 : u16 pci_find_ext_capability(struct pci_dev *dev, int cap);
1078 : u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 pos, int cap);
1079 : struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1080 :
1081 : u64 pci_get_dsn(struct pci_dev *dev);
1082 :
1083 : struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
1084 : struct pci_dev *from);
1085 : struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
1086 : unsigned int ss_vendor, unsigned int ss_device,
1087 : struct pci_dev *from);
1088 : struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
1089 : struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
1090 : unsigned int devfn);
1091 : struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
1092 : int pci_dev_present(const struct pci_device_id *ids);
1093 :
1094 : int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
1095 : int where, u8 *val);
1096 : int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
1097 : int where, u16 *val);
1098 : int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
1099 : int where, u32 *val);
1100 : int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
1101 : int where, u8 val);
1102 : int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
1103 : int where, u16 val);
1104 : int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
1105 : int where, u32 val);
1106 :
1107 : int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
1108 : int where, int size, u32 *val);
1109 : int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
1110 : int where, int size, u32 val);
1111 : int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
1112 : int where, int size, u32 *val);
1113 : int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
1114 : int where, int size, u32 val);
1115 :
1116 : struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1117 :
1118 : int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
1119 : int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
1120 : int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
1121 : int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
1122 : int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
1123 : int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
1124 :
1125 : int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
1126 : int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
1127 : int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
1128 : int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
1129 : int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
1130 : u16 clear, u16 set);
1131 : int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1132 : u32 clear, u32 set);
1133 :
1134 : static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1135 : u16 set)
1136 : {
1137 : return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1138 : }
1139 :
1140 : static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1141 : u32 set)
1142 : {
1143 : return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1144 : }
1145 :
1146 : static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1147 : u16 clear)
1148 : {
1149 : return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1150 : }
1151 :
1152 : static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1153 : u32 clear)
1154 : {
1155 : return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1156 : }
1157 :
1158 : /* User-space driven config access */
1159 : int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1160 : int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1161 : int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1162 : int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1163 : int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1164 : int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1165 :
1166 : int __must_check pci_enable_device(struct pci_dev *dev);
1167 : int __must_check pci_enable_device_io(struct pci_dev *dev);
1168 : int __must_check pci_enable_device_mem(struct pci_dev *dev);
1169 : int __must_check pci_reenable_device(struct pci_dev *);
1170 : int __must_check pcim_enable_device(struct pci_dev *pdev);
1171 : void pcim_pin_device(struct pci_dev *pdev);
1172 :
1173 : static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1174 : {
1175 : /*
1176 : * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
1177 : * writable and no quirk has marked the feature broken.
1178 : */
1179 : return !pdev->broken_intx_masking;
1180 : }
1181 :
1182 : static inline int pci_is_enabled(struct pci_dev *pdev)
1183 : {
1184 : return (atomic_read(&pdev->enable_cnt) > 0);
1185 : }
1186 :
1187 : static inline int pci_is_managed(struct pci_dev *pdev)
1188 : {
1189 : return pdev->is_managed;
1190 : }
1191 :
1192 : void pci_disable_device(struct pci_dev *dev);
1193 :
1194 : extern unsigned int pcibios_max_latency;
1195 : void pci_set_master(struct pci_dev *dev);
1196 : void pci_clear_master(struct pci_dev *dev);
1197 :
1198 : int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1199 : int pci_set_cacheline_size(struct pci_dev *dev);
1200 : int __must_check pci_set_mwi(struct pci_dev *dev);
1201 : int __must_check pcim_set_mwi(struct pci_dev *dev);
1202 : int pci_try_set_mwi(struct pci_dev *dev);
1203 : void pci_clear_mwi(struct pci_dev *dev);
1204 : void pci_intx(struct pci_dev *dev, int enable);
1205 : bool pci_check_and_mask_intx(struct pci_dev *dev);
1206 : bool pci_check_and_unmask_intx(struct pci_dev *dev);
1207 : int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1208 : int pci_wait_for_pending_transaction(struct pci_dev *dev);
1209 : int pcix_get_max_mmrbc(struct pci_dev *dev);
1210 : int pcix_get_mmrbc(struct pci_dev *dev);
1211 : int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1212 : int pcie_get_readrq(struct pci_dev *dev);
1213 : int pcie_set_readrq(struct pci_dev *dev, int rq);
1214 : int pcie_get_mps(struct pci_dev *dev);
1215 : int pcie_set_mps(struct pci_dev *dev, int mps);
1216 : u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
1217 : enum pci_bus_speed *speed,
1218 : enum pcie_link_width *width);
1219 : void pcie_print_link_status(struct pci_dev *dev);
1220 : bool pcie_has_flr(struct pci_dev *dev);
1221 : int pcie_flr(struct pci_dev *dev);
1222 : int __pci_reset_function_locked(struct pci_dev *dev);
1223 : int pci_reset_function(struct pci_dev *dev);
1224 : int pci_reset_function_locked(struct pci_dev *dev);
1225 : int pci_try_reset_function(struct pci_dev *dev);
1226 : int pci_probe_reset_slot(struct pci_slot *slot);
1227 : int pci_probe_reset_bus(struct pci_bus *bus);
1228 : int pci_reset_bus(struct pci_dev *dev);
1229 : void pci_reset_secondary_bus(struct pci_dev *dev);
1230 : void pcibios_reset_secondary_bus(struct pci_dev *dev);
1231 : void pci_update_resource(struct pci_dev *dev, int resno);
1232 : int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1233 : int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1234 : void pci_release_resource(struct pci_dev *dev, int resno);
1235 : static inline int pci_rebar_bytes_to_size(u64 bytes)
1236 : {
1237 : bytes = roundup_pow_of_two(bytes);
1238 :
1239 : /* Return BAR size as defined in the resizable BAR specification */
1240 : return max(ilog2(bytes), 20) - 20;
1241 : }
1242 :
1243 : u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar);
1244 : int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
1245 : int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1246 : bool pci_device_is_present(struct pci_dev *pdev);
1247 : void pci_ignore_hotplug(struct pci_dev *dev);
1248 : struct pci_dev *pci_real_dma_dev(struct pci_dev *dev);
1249 : int pci_status_get_and_clear_errors(struct pci_dev *pdev);
1250 :
1251 : int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1252 : irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1253 : const char *fmt, ...);
1254 : void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1255 :
1256 : /* ROM control related routines */
1257 : int pci_enable_rom(struct pci_dev *pdev);
1258 : void pci_disable_rom(struct pci_dev *pdev);
1259 : void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1260 : void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1261 :
1262 : /* Power management related routines */
1263 : int pci_save_state(struct pci_dev *dev);
1264 : void pci_restore_state(struct pci_dev *dev);
1265 : struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1266 : int pci_load_saved_state(struct pci_dev *dev,
1267 : struct pci_saved_state *state);
1268 : int pci_load_and_free_saved_state(struct pci_dev *dev,
1269 : struct pci_saved_state **state);
1270 : struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1271 : struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1272 : u16 cap);
1273 : int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1274 : int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1275 : u16 cap, unsigned int size);
1276 : int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state);
1277 : int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1278 : pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1279 : bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1280 : void pci_pme_active(struct pci_dev *dev, bool enable);
1281 : int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
1282 : int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1283 : int pci_prepare_to_sleep(struct pci_dev *dev);
1284 : int pci_back_from_sleep(struct pci_dev *dev);
1285 : bool pci_dev_run_wake(struct pci_dev *dev);
1286 : void pci_d3cold_enable(struct pci_dev *dev);
1287 : void pci_d3cold_disable(struct pci_dev *dev);
1288 : bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
1289 : void pci_resume_bus(struct pci_bus *bus);
1290 : void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
1291 :
1292 : /* For use by arch with custom probe code */
1293 : void set_pcie_port_type(struct pci_dev *pdev);
1294 : void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1295 :
1296 : /* Functions for PCI Hotplug drivers to use */
1297 : unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1298 : unsigned int pci_rescan_bus(struct pci_bus *bus);
1299 : void pci_lock_rescan_remove(void);
1300 : void pci_unlock_rescan_remove(void);
1301 :
1302 : /* Vital Product Data routines */
1303 : ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1304 : ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1305 : int pci_set_vpd_size(struct pci_dev *dev, size_t len);
1306 :
1307 : /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1308 : resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1309 : void pci_bus_assign_resources(const struct pci_bus *bus);
1310 : void pci_bus_claim_resources(struct pci_bus *bus);
1311 : void pci_bus_size_bridges(struct pci_bus *bus);
1312 : int pci_claim_resource(struct pci_dev *, int);
1313 : int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1314 : void pci_assign_unassigned_resources(void);
1315 : void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1316 : void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1317 : void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1318 : int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
1319 : void pdev_enable_device(struct pci_dev *);
1320 : int pci_enable_resources(struct pci_dev *, int mask);
1321 : void pci_assign_irq(struct pci_dev *dev);
1322 : struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1323 : #define HAVE_PCI_REQ_REGIONS 2
1324 : int __must_check pci_request_regions(struct pci_dev *, const char *);
1325 : int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1326 : void pci_release_regions(struct pci_dev *);
1327 : int __must_check pci_request_region(struct pci_dev *, int, const char *);
1328 : void pci_release_region(struct pci_dev *, int);
1329 : int pci_request_selected_regions(struct pci_dev *, int, const char *);
1330 : int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1331 : void pci_release_selected_regions(struct pci_dev *, int);
1332 :
1333 : /* drivers/pci/bus.c */
1334 : void pci_add_resource(struct list_head *resources, struct resource *res);
1335 : void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1336 : resource_size_t offset);
1337 : void pci_free_resource_list(struct list_head *resources);
1338 : void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1339 : unsigned int flags);
1340 : struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1341 : void pci_bus_remove_resources(struct pci_bus *bus);
1342 : int devm_request_pci_bus_resources(struct device *dev,
1343 : struct list_head *resources);
1344 :
1345 : /* Temporary until new and working PCI SBR API in place */
1346 : int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
1347 :
1348 : #define pci_bus_for_each_resource(bus, res, i) \
1349 : for (i = 0; \
1350 : (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1351 : i++)
1352 :
1353 : int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1354 : struct resource *res, resource_size_t size,
1355 : resource_size_t align, resource_size_t min,
1356 : unsigned long type_mask,
1357 : resource_size_t (*alignf)(void *,
1358 : const struct resource *,
1359 : resource_size_t,
1360 : resource_size_t),
1361 : void *alignf_data);
1362 :
1363 :
1364 : int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
1365 : resource_size_t size);
1366 : unsigned long pci_address_to_pio(phys_addr_t addr);
1367 : phys_addr_t pci_pio_to_address(unsigned long pio);
1368 : int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1369 : int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
1370 : phys_addr_t phys_addr);
1371 : void pci_unmap_iospace(struct resource *res);
1372 : void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1373 : resource_size_t offset,
1374 : resource_size_t size);
1375 : void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1376 : struct resource *res);
1377 :
1378 : static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1379 : {
1380 : struct pci_bus_region region;
1381 :
1382 : pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1383 : return region.start;
1384 : }
1385 :
1386 : /* Proper probing supporting hot-pluggable devices */
1387 : int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1388 : const char *mod_name);
1389 :
1390 : /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */
1391 : #define pci_register_driver(driver) \
1392 : __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1393 :
1394 : void pci_unregister_driver(struct pci_driver *dev);
1395 :
1396 : /**
1397 : * module_pci_driver() - Helper macro for registering a PCI driver
1398 : * @__pci_driver: pci_driver struct
1399 : *
1400 : * Helper macro for PCI drivers which do not do anything special in module
1401 : * init/exit. This eliminates a lot of boilerplate. Each module may only
1402 : * use this macro once, and calling it replaces module_init() and module_exit()
1403 : */
1404 : #define module_pci_driver(__pci_driver) \
1405 : module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
1406 :
1407 : /**
1408 : * builtin_pci_driver() - Helper macro for registering a PCI driver
1409 : * @__pci_driver: pci_driver struct
1410 : *
1411 : * Helper macro for PCI drivers which do not do anything special in their
1412 : * init code. This eliminates a lot of boilerplate. Each driver may only
1413 : * use this macro once, and calling it replaces device_initcall(...)
1414 : */
1415 : #define builtin_pci_driver(__pci_driver) \
1416 : builtin_driver(__pci_driver, pci_register_driver)
1417 :
1418 : struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1419 : int pci_add_dynid(struct pci_driver *drv,
1420 : unsigned int vendor, unsigned int device,
1421 : unsigned int subvendor, unsigned int subdevice,
1422 : unsigned int class, unsigned int class_mask,
1423 : unsigned long driver_data);
1424 : const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1425 : struct pci_dev *dev);
1426 : int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1427 : int pass);
1428 :
1429 : void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1430 : void *userdata);
1431 : int pci_cfg_space_size(struct pci_dev *dev);
1432 : unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1433 : void pci_setup_bridge(struct pci_bus *bus);
1434 : resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1435 : unsigned long type);
1436 :
1437 : #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1438 : #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1439 :
1440 : int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1441 : unsigned int command_bits, u32 flags);
1442 :
1443 : /*
1444 : * Virtual interrupts allow for more interrupts to be allocated
1445 : * than the device has interrupts for. These are not programmed
1446 : * into the device's MSI-X table and must be handled by some
1447 : * other driver means.
1448 : */
1449 : #define PCI_IRQ_VIRTUAL (1 << 4)
1450 :
1451 : #define PCI_IRQ_ALL_TYPES \
1452 : (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1453 :
1454 : /* kmem_cache style wrapper around pci_alloc_consistent() */
1455 :
1456 : #include <linux/dmapool.h>
1457 :
1458 : #define pci_pool dma_pool
1459 : #define pci_pool_create(name, pdev, size, align, allocation) \
1460 : dma_pool_create(name, &pdev->dev, size, align, allocation)
1461 : #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1462 : #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1463 : #define pci_pool_zalloc(pool, flags, handle) \
1464 : dma_pool_zalloc(pool, flags, handle)
1465 : #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1466 :
1467 : struct msix_entry {
1468 : u32 vector; /* Kernel uses to write allocated vector */
1469 : u16 entry; /* Driver uses to specify entry, OS writes */
1470 : };
1471 :
1472 : #ifdef CONFIG_PCI_MSI
1473 : int pci_msi_vec_count(struct pci_dev *dev);
1474 : void pci_disable_msi(struct pci_dev *dev);
1475 : int pci_msix_vec_count(struct pci_dev *dev);
1476 : void pci_disable_msix(struct pci_dev *dev);
1477 : void pci_restore_msi_state(struct pci_dev *dev);
1478 : int pci_msi_enabled(void);
1479 : int pci_enable_msi(struct pci_dev *dev);
1480 : int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1481 : int minvec, int maxvec);
1482 : static inline int pci_enable_msix_exact(struct pci_dev *dev,
1483 : struct msix_entry *entries, int nvec)
1484 : {
1485 : int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1486 : if (rc < 0)
1487 : return rc;
1488 : return 0;
1489 : }
1490 : int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1491 : unsigned int max_vecs, unsigned int flags,
1492 : struct irq_affinity *affd);
1493 :
1494 : void pci_free_irq_vectors(struct pci_dev *dev);
1495 : int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1496 : const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1497 :
1498 : #else
1499 : static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1500 : static inline void pci_disable_msi(struct pci_dev *dev) { }
1501 : static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1502 : static inline void pci_disable_msix(struct pci_dev *dev) { }
1503 : static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1504 : static inline int pci_msi_enabled(void) { return 0; }
1505 : static inline int pci_enable_msi(struct pci_dev *dev)
1506 : { return -ENOSYS; }
1507 : static inline int pci_enable_msix_range(struct pci_dev *dev,
1508 : struct msix_entry *entries, int minvec, int maxvec)
1509 : { return -ENOSYS; }
1510 : static inline int pci_enable_msix_exact(struct pci_dev *dev,
1511 : struct msix_entry *entries, int nvec)
1512 : { return -ENOSYS; }
1513 :
1514 : static inline int
1515 : pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1516 : unsigned int max_vecs, unsigned int flags,
1517 : struct irq_affinity *aff_desc)
1518 : {
1519 : if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1520 : return 1;
1521 : return -ENOSPC;
1522 : }
1523 :
1524 : static inline void pci_free_irq_vectors(struct pci_dev *dev)
1525 : {
1526 : }
1527 :
1528 : static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1529 : {
1530 : if (WARN_ON_ONCE(nr > 0))
1531 : return -EINVAL;
1532 : return dev->irq;
1533 : }
1534 : static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1535 : int vec)
1536 : {
1537 : return cpu_possible_mask;
1538 : }
1539 : #endif
1540 :
1541 : /**
1542 : * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
1543 : * @d: the INTx IRQ domain
1544 : * @node: the DT node for the device whose interrupt we're translating
1545 : * @intspec: the interrupt specifier data from the DT
1546 : * @intsize: the number of entries in @intspec
1547 : * @out_hwirq: pointer at which to write the hwirq number
1548 : * @out_type: pointer at which to write the interrupt type
1549 : *
1550 : * Translate a PCI INTx interrupt number from device tree in the range 1-4, as
1551 : * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range
1552 : * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the
1553 : * INTx value to obtain the hwirq number.
1554 : *
1555 : * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range.
1556 : */
1557 : static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1558 : struct device_node *node,
1559 : const u32 *intspec,
1560 : unsigned int intsize,
1561 : unsigned long *out_hwirq,
1562 : unsigned int *out_type)
1563 : {
1564 : const u32 intx = intspec[0];
1565 :
1566 : if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1567 : return -EINVAL;
1568 :
1569 : *out_hwirq = intx - PCI_INTERRUPT_INTA;
1570 : return 0;
1571 : }
1572 :
1573 : #ifdef CONFIG_PCIEPORTBUS
1574 : extern bool pcie_ports_disabled;
1575 : extern bool pcie_ports_native;
1576 : #else
1577 : #define pcie_ports_disabled true
1578 : #define pcie_ports_native false
1579 : #endif
1580 :
1581 : #define PCIE_LINK_STATE_L0S BIT(0)
1582 : #define PCIE_LINK_STATE_L1 BIT(1)
1583 : #define PCIE_LINK_STATE_CLKPM BIT(2)
1584 : #define PCIE_LINK_STATE_L1_1 BIT(3)
1585 : #define PCIE_LINK_STATE_L1_2 BIT(4)
1586 : #define PCIE_LINK_STATE_L1_1_PCIPM BIT(5)
1587 : #define PCIE_LINK_STATE_L1_2_PCIPM BIT(6)
1588 :
1589 : #ifdef CONFIG_PCIEASPM
1590 : int pci_disable_link_state(struct pci_dev *pdev, int state);
1591 : int pci_disable_link_state_locked(struct pci_dev *pdev, int state);
1592 : void pcie_no_aspm(void);
1593 : bool pcie_aspm_support_enabled(void);
1594 : bool pcie_aspm_enabled(struct pci_dev *pdev);
1595 : #else
1596 : static inline int pci_disable_link_state(struct pci_dev *pdev, int state)
1597 : { return 0; }
1598 : static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state)
1599 : { return 0; }
1600 : static inline void pcie_no_aspm(void) { }
1601 : static inline bool pcie_aspm_support_enabled(void) { return false; }
1602 : static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; }
1603 : #endif
1604 :
1605 : #ifdef CONFIG_PCIEAER
1606 : bool pci_aer_available(void);
1607 : #else
1608 : static inline bool pci_aer_available(void) { return false; }
1609 : #endif
1610 :
1611 : bool pci_ats_disabled(void);
1612 :
1613 : void pci_cfg_access_lock(struct pci_dev *dev);
1614 : bool pci_cfg_access_trylock(struct pci_dev *dev);
1615 : void pci_cfg_access_unlock(struct pci_dev *dev);
1616 :
1617 : /*
1618 : * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1619 : * a PCI domain is defined to be a set of PCI buses which share
1620 : * configuration space.
1621 : */
1622 : #ifdef CONFIG_PCI_DOMAINS
1623 : extern int pci_domains_supported;
1624 : #else
1625 : enum { pci_domains_supported = 0 };
1626 : static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1627 : static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1628 : #endif /* CONFIG_PCI_DOMAINS */
1629 :
1630 : /*
1631 : * Generic implementation for PCI domain support. If your
1632 : * architecture does not need custom management of PCI
1633 : * domains then this implementation will be used
1634 : */
1635 : #ifdef CONFIG_PCI_DOMAINS_GENERIC
1636 : static inline int pci_domain_nr(struct pci_bus *bus)
1637 : {
1638 : return bus->domain_nr;
1639 : }
1640 : #ifdef CONFIG_ACPI
1641 : int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1642 : #else
1643 : static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1644 : { return 0; }
1645 : #endif
1646 : int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1647 : #endif
1648 :
1649 : /* Some architectures require additional setup to direct VGA traffic */
1650 : typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1651 : unsigned int command_bits, u32 flags);
1652 : void pci_register_set_vga_state(arch_set_vga_state_t func);
1653 :
1654 : static inline int
1655 : pci_request_io_regions(struct pci_dev *pdev, const char *name)
1656 : {
1657 : return pci_request_selected_regions(pdev,
1658 : pci_select_bars(pdev, IORESOURCE_IO), name);
1659 : }
1660 :
1661 : static inline void
1662 : pci_release_io_regions(struct pci_dev *pdev)
1663 : {
1664 : return pci_release_selected_regions(pdev,
1665 : pci_select_bars(pdev, IORESOURCE_IO));
1666 : }
1667 :
1668 : static inline int
1669 : pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1670 : {
1671 : return pci_request_selected_regions(pdev,
1672 : pci_select_bars(pdev, IORESOURCE_MEM), name);
1673 : }
1674 :
1675 : static inline void
1676 : pci_release_mem_regions(struct pci_dev *pdev)
1677 : {
1678 : return pci_release_selected_regions(pdev,
1679 : pci_select_bars(pdev, IORESOURCE_MEM));
1680 : }
1681 :
1682 : #else /* CONFIG_PCI is not enabled */
1683 :
1684 : static inline void pci_set_flags(int flags) { }
1685 : static inline void pci_add_flags(int flags) { }
1686 : static inline void pci_clear_flags(int flags) { }
1687 : static inline int pci_has_flag(int flag) { return 0; }
1688 :
1689 : /*
1690 : * If the system does not have PCI, clearly these return errors. Define
1691 : * these as simple inline functions to avoid hair in drivers.
1692 : */
1693 : #define _PCI_NOP(o, s, t) \
1694 : static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1695 : int where, t val) \
1696 : { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1697 :
1698 : #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1699 : _PCI_NOP(o, word, u16 x) \
1700 : _PCI_NOP(o, dword, u32 x)
1701 0 : _PCI_NOP_ALL(read, *)
1702 0 : _PCI_NOP_ALL(write,)
1703 :
1704 0 : static inline struct pci_dev *pci_get_device(unsigned int vendor,
1705 : unsigned int device,
1706 : struct pci_dev *from)
1707 0 : { return NULL; }
1708 :
1709 : static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1710 : unsigned int device,
1711 : unsigned int ss_vendor,
1712 : unsigned int ss_device,
1713 : struct pci_dev *from)
1714 : { return NULL; }
1715 :
1716 0 : static inline struct pci_dev *pci_get_class(unsigned int class,
1717 : struct pci_dev *from)
1718 0 : { return NULL; }
1719 :
1720 : #define pci_dev_present(ids) (0)
1721 : #define no_pci_devices() (1)
1722 : #define pci_dev_put(dev) do { } while (0)
1723 :
1724 : static inline void pci_set_master(struct pci_dev *dev) { }
1725 : static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1726 : static inline void pci_disable_device(struct pci_dev *dev) { }
1727 : static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; }
1728 : static inline int pci_assign_resource(struct pci_dev *dev, int i)
1729 : { return -EBUSY; }
1730 : static inline int __pci_register_driver(struct pci_driver *drv,
1731 : struct module *owner)
1732 : { return 0; }
1733 : static inline int pci_register_driver(struct pci_driver *drv)
1734 : { return 0; }
1735 : static inline void pci_unregister_driver(struct pci_driver *drv) { }
1736 : static inline u8 pci_find_capability(struct pci_dev *dev, int cap)
1737 : { return 0; }
1738 : static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1739 : int cap)
1740 : { return 0; }
1741 : static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1742 : { return 0; }
1743 :
1744 : static inline u64 pci_get_dsn(struct pci_dev *dev)
1745 : { return 0; }
1746 :
1747 : /* Power management related routines */
1748 : static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1749 : static inline void pci_restore_state(struct pci_dev *dev) { }
1750 : static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1751 : { return 0; }
1752 : static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1753 : { return 0; }
1754 : static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1755 : pm_message_t state)
1756 : { return PCI_D0; }
1757 : static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1758 : int enable)
1759 : { return 0; }
1760 :
1761 : static inline struct resource *pci_find_resource(struct pci_dev *dev,
1762 : struct resource *res)
1763 : { return NULL; }
1764 : static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1765 : { return -EIO; }
1766 : static inline void pci_release_regions(struct pci_dev *dev) { }
1767 :
1768 : static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1769 :
1770 : static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1771 : { return NULL; }
1772 : static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1773 : unsigned int devfn)
1774 : { return NULL; }
1775 : static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
1776 : unsigned int bus, unsigned int devfn)
1777 : { return NULL; }
1778 :
1779 : static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1780 : static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1781 :
1782 : #define dev_is_pci(d) (false)
1783 : #define dev_is_pf(d) (false)
1784 : static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
1785 : { return false; }
1786 : static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1787 : struct device_node *node,
1788 : const u32 *intspec,
1789 : unsigned int intsize,
1790 : unsigned long *out_hwirq,
1791 : unsigned int *out_type)
1792 : { return -EINVAL; }
1793 :
1794 : static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1795 : struct pci_dev *dev)
1796 : { return NULL; }
1797 : static inline bool pci_ats_disabled(void) { return true; }
1798 :
1799 : static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1800 : {
1801 : return -EINVAL;
1802 : }
1803 :
1804 : static inline int
1805 : pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1806 : unsigned int max_vecs, unsigned int flags,
1807 : struct irq_affinity *aff_desc)
1808 : {
1809 : return -ENOSPC;
1810 : }
1811 : #endif /* CONFIG_PCI */
1812 :
1813 : static inline int
1814 : pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1815 : unsigned int max_vecs, unsigned int flags)
1816 : {
1817 : return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
1818 : NULL);
1819 : }
1820 :
1821 : /* Include architecture-dependent settings and functions */
1822 :
1823 : #include <asm/pci.h>
1824 :
1825 : /* These two functions provide almost identical functionality. Depending
1826 : * on the architecture, one will be implemented as a wrapper around the
1827 : * other (in drivers/pci/mmap.c).
1828 : *
1829 : * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
1830 : * is expected to be an offset within that region.
1831 : *
1832 : * pci_mmap_page_range() is the legacy architecture-specific interface,
1833 : * which accepts a "user visible" resource address converted by
1834 : * pci_resource_to_user(), as used in the legacy mmap() interface in
1835 : * /proc/bus/pci/.
1836 : */
1837 : int pci_mmap_resource_range(struct pci_dev *dev, int bar,
1838 : struct vm_area_struct *vma,
1839 : enum pci_mmap_state mmap_state, int write_combine);
1840 : int pci_mmap_page_range(struct pci_dev *pdev, int bar,
1841 : struct vm_area_struct *vma,
1842 : enum pci_mmap_state mmap_state, int write_combine);
1843 :
1844 : #ifndef arch_can_pci_mmap_wc
1845 : #define arch_can_pci_mmap_wc() 0
1846 : #endif
1847 :
1848 : #ifndef arch_can_pci_mmap_io
1849 : #define arch_can_pci_mmap_io() 0
1850 : #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1851 : #else
1852 : int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
1853 : #endif
1854 :
1855 : #ifndef pci_root_bus_fwnode
1856 : #define pci_root_bus_fwnode(bus) NULL
1857 : #endif
1858 :
1859 : /*
1860 : * These helpers provide future and backwards compatibility
1861 : * for accessing popular PCI BAR info
1862 : */
1863 : #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1864 : #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1865 : #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1866 : #define pci_resource_len(dev,bar) \
1867 : ((pci_resource_start((dev), (bar)) == 0 && \
1868 : pci_resource_end((dev), (bar)) == \
1869 : pci_resource_start((dev), (bar))) ? 0 : \
1870 : \
1871 : (pci_resource_end((dev), (bar)) - \
1872 : pci_resource_start((dev), (bar)) + 1))
1873 :
1874 : /*
1875 : * Similar to the helpers above, these manipulate per-pci_dev
1876 : * driver-specific data. They are really just a wrapper around
1877 : * the generic device structure functions of these calls.
1878 : */
1879 : static inline void *pci_get_drvdata(struct pci_dev *pdev)
1880 : {
1881 : return dev_get_drvdata(&pdev->dev);
1882 : }
1883 :
1884 : static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1885 : {
1886 : dev_set_drvdata(&pdev->dev, data);
1887 : }
1888 :
1889 : static inline const char *pci_name(const struct pci_dev *pdev)
1890 : {
1891 : return dev_name(&pdev->dev);
1892 : }
1893 :
1894 : void pci_resource_to_user(const struct pci_dev *dev, int bar,
1895 : const struct resource *rsrc,
1896 : resource_size_t *start, resource_size_t *end);
1897 :
1898 : /*
1899 : * The world is not perfect and supplies us with broken PCI devices.
1900 : * For at least a part of these bugs we need a work-around, so both
1901 : * generic (drivers/pci/quirks.c) and per-architecture code can define
1902 : * fixup hooks to be called for particular buggy devices.
1903 : */
1904 :
1905 : struct pci_fixup {
1906 : u16 vendor; /* Or PCI_ANY_ID */
1907 : u16 device; /* Or PCI_ANY_ID */
1908 : u32 class; /* Or PCI_ANY_ID */
1909 : unsigned int class_shift; /* should be 0, 8, 16 */
1910 : #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1911 : int hook_offset;
1912 : #else
1913 : void (*hook)(struct pci_dev *dev);
1914 : #endif
1915 : };
1916 :
1917 : enum pci_fixup_pass {
1918 : pci_fixup_early, /* Before probing BARs */
1919 : pci_fixup_header, /* After reading configuration header */
1920 : pci_fixup_final, /* Final phase of device fixups */
1921 : pci_fixup_enable, /* pci_enable_device() time */
1922 : pci_fixup_resume, /* pci_device_resume() */
1923 : pci_fixup_suspend, /* pci_device_suspend() */
1924 : pci_fixup_resume_early, /* pci_device_resume_early() */
1925 : pci_fixup_suspend_late, /* pci_device_suspend_late() */
1926 : };
1927 :
1928 : #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1929 : #define ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1930 : class_shift, hook) \
1931 : __ADDRESSABLE(hook) \
1932 : asm(".section " #sec ", \"a\" \n" \
1933 : ".balign 16 \n" \
1934 : ".short " #vendor ", " #device " \n" \
1935 : ".long " #class ", " #class_shift " \n" \
1936 : ".long " #hook " - . \n" \
1937 : ".previous \n");
1938 :
1939 : /*
1940 : * Clang's LTO may rename static functions in C, but has no way to
1941 : * handle such renamings when referenced from inline asm. To work
1942 : * around this, create global C stubs for these cases.
1943 : */
1944 : #ifdef CONFIG_LTO_CLANG
1945 : #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1946 : class_shift, hook, stub) \
1947 : void stub(struct pci_dev *dev); \
1948 : void stub(struct pci_dev *dev) \
1949 : { \
1950 : hook(dev); \
1951 : } \
1952 : ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1953 : class_shift, stub)
1954 : #else
1955 : #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1956 : class_shift, hook, stub) \
1957 : ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1958 : class_shift, hook)
1959 : #endif
1960 :
1961 : #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1962 : class_shift, hook) \
1963 : __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1964 : class_shift, hook, __UNIQUE_ID(hook))
1965 : #else
1966 : /* Anonymous variables would be nice... */
1967 : #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1968 : class_shift, hook) \
1969 : static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
1970 : __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1971 : = { vendor, device, class, class_shift, hook };
1972 : #endif
1973 :
1974 : #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1975 : class_shift, hook) \
1976 : DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1977 : hook, vendor, device, class, class_shift, hook)
1978 : #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1979 : class_shift, hook) \
1980 : DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1981 : hook, vendor, device, class, class_shift, hook)
1982 : #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1983 : class_shift, hook) \
1984 : DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1985 : hook, vendor, device, class, class_shift, hook)
1986 : #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1987 : class_shift, hook) \
1988 : DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1989 : hook, vendor, device, class, class_shift, hook)
1990 : #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1991 : class_shift, hook) \
1992 : DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1993 : resume##hook, vendor, device, class, class_shift, hook)
1994 : #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1995 : class_shift, hook) \
1996 : DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1997 : resume_early##hook, vendor, device, class, class_shift, hook)
1998 : #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1999 : class_shift, hook) \
2000 : DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
2001 : suspend##hook, vendor, device, class, class_shift, hook)
2002 : #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
2003 : class_shift, hook) \
2004 : DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
2005 : suspend_late##hook, vendor, device, class, class_shift, hook)
2006 :
2007 : #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
2008 : DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
2009 : hook, vendor, device, PCI_ANY_ID, 0, hook)
2010 : #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
2011 : DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
2012 : hook, vendor, device, PCI_ANY_ID, 0, hook)
2013 : #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
2014 : DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
2015 : hook, vendor, device, PCI_ANY_ID, 0, hook)
2016 : #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
2017 : DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
2018 : hook, vendor, device, PCI_ANY_ID, 0, hook)
2019 : #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
2020 : DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
2021 : resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
2022 : #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
2023 : DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
2024 : resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
2025 : #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
2026 : DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
2027 : suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
2028 : #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
2029 : DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
2030 : suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
2031 :
2032 : #ifdef CONFIG_PCI_QUIRKS
2033 : void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
2034 : #else
2035 : static inline void pci_fixup_device(enum pci_fixup_pass pass,
2036 : struct pci_dev *dev) { }
2037 : #endif
2038 :
2039 : void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
2040 : void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
2041 : void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
2042 : int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
2043 : int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
2044 : const char *name);
2045 : void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
2046 :
2047 : extern int pci_pci_problems;
2048 : #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
2049 : #define PCIPCI_TRITON 2
2050 : #define PCIPCI_NATOMA 4
2051 : #define PCIPCI_VIAETBF 8
2052 : #define PCIPCI_VSFX 16
2053 : #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
2054 : #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
2055 :
2056 : extern unsigned long pci_cardbus_io_size;
2057 : extern unsigned long pci_cardbus_mem_size;
2058 : extern u8 pci_dfl_cache_line_size;
2059 : extern u8 pci_cache_line_size;
2060 :
2061 : /* Architecture-specific versions may override these (weak) */
2062 : void pcibios_disable_device(struct pci_dev *dev);
2063 : void pcibios_set_master(struct pci_dev *dev);
2064 : int pcibios_set_pcie_reset_state(struct pci_dev *dev,
2065 : enum pcie_reset_state state);
2066 : int pcibios_add_device(struct pci_dev *dev);
2067 : void pcibios_release_device(struct pci_dev *dev);
2068 : #ifdef CONFIG_PCI
2069 : void pcibios_penalize_isa_irq(int irq, int active);
2070 : #else
2071 : static inline void pcibios_penalize_isa_irq(int irq, int active) {}
2072 : #endif
2073 : int pcibios_alloc_irq(struct pci_dev *dev);
2074 : void pcibios_free_irq(struct pci_dev *dev);
2075 : resource_size_t pcibios_default_alignment(void);
2076 :
2077 : #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
2078 : void __init pci_mmcfg_early_init(void);
2079 : void __init pci_mmcfg_late_init(void);
2080 : #else
2081 : static inline void pci_mmcfg_early_init(void) { }
2082 : static inline void pci_mmcfg_late_init(void) { }
2083 : #endif
2084 :
2085 : int pci_ext_cfg_avail(void);
2086 :
2087 : void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
2088 : void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
2089 :
2090 : #ifdef CONFIG_PCI_IOV
2091 : int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
2092 : int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
2093 :
2094 : int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
2095 : void pci_disable_sriov(struct pci_dev *dev);
2096 :
2097 : int pci_iov_sysfs_link(struct pci_dev *dev, struct pci_dev *virtfn, int id);
2098 : int pci_iov_add_virtfn(struct pci_dev *dev, int id);
2099 : void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
2100 : int pci_num_vf(struct pci_dev *dev);
2101 : int pci_vfs_assigned(struct pci_dev *dev);
2102 : int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
2103 : int pci_sriov_get_totalvfs(struct pci_dev *dev);
2104 : int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
2105 : resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
2106 : void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
2107 :
2108 : /* Arch may override these (weak) */
2109 : int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
2110 : int pcibios_sriov_disable(struct pci_dev *pdev);
2111 : resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
2112 : #else
2113 : static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
2114 : {
2115 : return -ENOSYS;
2116 : }
2117 : static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
2118 : {
2119 : return -ENOSYS;
2120 : }
2121 : static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
2122 : { return -ENODEV; }
2123 :
2124 : static inline int pci_iov_sysfs_link(struct pci_dev *dev,
2125 : struct pci_dev *virtfn, int id)
2126 : {
2127 : return -ENODEV;
2128 : }
2129 : static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
2130 : {
2131 : return -ENOSYS;
2132 : }
2133 : static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
2134 : int id) { }
2135 : static inline void pci_disable_sriov(struct pci_dev *dev) { }
2136 : static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
2137 : static inline int pci_vfs_assigned(struct pci_dev *dev)
2138 : { return 0; }
2139 : static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
2140 : { return 0; }
2141 : static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
2142 : { return 0; }
2143 : #define pci_sriov_configure_simple NULL
2144 : static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
2145 : { return 0; }
2146 : static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
2147 : #endif
2148 :
2149 : #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
2150 : void pci_hp_create_module_link(struct pci_slot *pci_slot);
2151 : void pci_hp_remove_module_link(struct pci_slot *pci_slot);
2152 : #endif
2153 :
2154 : /**
2155 : * pci_pcie_cap - get the saved PCIe capability offset
2156 : * @dev: PCI device
2157 : *
2158 : * PCIe capability offset is calculated at PCI device initialization
2159 : * time and saved in the data structure. This function returns saved
2160 : * PCIe capability offset. Using this instead of pci_find_capability()
2161 : * reduces unnecessary search in the PCI configuration space. If you
2162 : * need to calculate PCIe capability offset from raw device for some
2163 : * reasons, please use pci_find_capability() instead.
2164 : */
2165 : static inline int pci_pcie_cap(struct pci_dev *dev)
2166 : {
2167 : return dev->pcie_cap;
2168 : }
2169 :
2170 : /**
2171 : * pci_is_pcie - check if the PCI device is PCI Express capable
2172 : * @dev: PCI device
2173 : *
2174 : * Returns: true if the PCI device is PCI Express capable, false otherwise.
2175 : */
2176 : static inline bool pci_is_pcie(struct pci_dev *dev)
2177 : {
2178 : return pci_pcie_cap(dev);
2179 : }
2180 :
2181 : /**
2182 : * pcie_caps_reg - get the PCIe Capabilities Register
2183 : * @dev: PCI device
2184 : */
2185 : static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2186 : {
2187 : return dev->pcie_flags_reg;
2188 : }
2189 :
2190 : /**
2191 : * pci_pcie_type - get the PCIe device/port type
2192 : * @dev: PCI device
2193 : */
2194 : static inline int pci_pcie_type(const struct pci_dev *dev)
2195 : {
2196 : return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
2197 : }
2198 :
2199 : /**
2200 : * pcie_find_root_port - Get the PCIe root port device
2201 : * @dev: PCI device
2202 : *
2203 : * Traverse up the parent chain and return the PCIe Root Port PCI Device
2204 : * for a given PCI/PCIe Device.
2205 : */
2206 : static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2207 : {
2208 : while (dev) {
2209 : if (pci_is_pcie(dev) &&
2210 : pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2211 : return dev;
2212 : dev = pci_upstream_bridge(dev);
2213 : }
2214 :
2215 : return NULL;
2216 : }
2217 :
2218 : void pci_request_acs(void);
2219 : bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2220 : bool pci_acs_path_enabled(struct pci_dev *start,
2221 : struct pci_dev *end, u16 acs_flags);
2222 : int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
2223 :
2224 : #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
2225 : #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
2226 :
2227 : /* Large Resource Data Type Tag Item Names */
2228 : #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
2229 : #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
2230 : #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
2231 :
2232 : #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2233 : #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2234 : #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2235 :
2236 : /* Small Resource Data Type Tag Item Names */
2237 : #define PCI_VPD_STIN_END 0x0f /* End */
2238 :
2239 : #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3)
2240 :
2241 : #define PCI_VPD_SRDT_TIN_MASK 0x78
2242 : #define PCI_VPD_SRDT_LEN_MASK 0x07
2243 : #define PCI_VPD_LRDT_TIN_MASK 0x7f
2244 :
2245 : #define PCI_VPD_LRDT_TAG_SIZE 3
2246 : #define PCI_VPD_SRDT_TAG_SIZE 1
2247 :
2248 : #define PCI_VPD_INFO_FLD_HDR_SIZE 3
2249 :
2250 : #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2251 : #define PCI_VPD_RO_KEYWORD_SERIALNO "SN"
2252 : #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2253 : #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
2254 : #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
2255 :
2256 : /**
2257 : * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
2258 : * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2259 : *
2260 : * Returns the extracted Large Resource Data Type length.
2261 : */
2262 : static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
2263 : {
2264 : return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
2265 : }
2266 :
2267 : /**
2268 : * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item
2269 : * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2270 : *
2271 : * Returns the extracted Large Resource Data Type Tag item.
2272 : */
2273 : static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
2274 : {
2275 : return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
2276 : }
2277 :
2278 : /**
2279 : * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
2280 : * @srdt: Pointer to the beginning of the Small Resource Data Type tag
2281 : *
2282 : * Returns the extracted Small Resource Data Type length.
2283 : */
2284 : static inline u8 pci_vpd_srdt_size(const u8 *srdt)
2285 : {
2286 : return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
2287 : }
2288 :
2289 : /**
2290 : * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item
2291 : * @srdt: Pointer to the beginning of the Small Resource Data Type tag
2292 : *
2293 : * Returns the extracted Small Resource Data Type Tag Item.
2294 : */
2295 : static inline u8 pci_vpd_srdt_tag(const u8 *srdt)
2296 : {
2297 : return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3;
2298 : }
2299 :
2300 : /**
2301 : * pci_vpd_info_field_size - Extracts the information field length
2302 : * @info_field: Pointer to the beginning of an information field header
2303 : *
2304 : * Returns the extracted information field length.
2305 : */
2306 : static inline u8 pci_vpd_info_field_size(const u8 *info_field)
2307 : {
2308 : return info_field[2];
2309 : }
2310 :
2311 : /**
2312 : * pci_vpd_find_tag - Locates the Resource Data Type tag provided
2313 : * @buf: Pointer to buffered vpd data
2314 : * @off: The offset into the buffer at which to begin the search
2315 : * @len: The length of the vpd buffer
2316 : * @rdt: The Resource Data Type to search for
2317 : *
2318 : * Returns the index where the Resource Data Type was found or
2319 : * -ENOENT otherwise.
2320 : */
2321 : int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
2322 :
2323 : /**
2324 : * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
2325 : * @buf: Pointer to buffered vpd data
2326 : * @off: The offset into the buffer at which to begin the search
2327 : * @len: The length of the buffer area, relative to off, in which to search
2328 : * @kw: The keyword to search for
2329 : *
2330 : * Returns the index where the information field keyword was found or
2331 : * -ENOENT otherwise.
2332 : */
2333 : int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
2334 : unsigned int len, const char *kw);
2335 :
2336 : /* PCI <-> OF binding helpers */
2337 : #ifdef CONFIG_OF
2338 : struct device_node;
2339 : struct irq_domain;
2340 : struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2341 :
2342 : /* Arch may override this (weak) */
2343 : struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2344 :
2345 : #else /* CONFIG_OF */
2346 : static inline struct irq_domain *
2347 : pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
2348 : #endif /* CONFIG_OF */
2349 :
2350 : static inline struct device_node *
2351 : pci_device_to_OF_node(const struct pci_dev *pdev)
2352 : {
2353 : return pdev ? pdev->dev.of_node : NULL;
2354 : }
2355 :
2356 : static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2357 : {
2358 : return bus ? bus->dev.of_node : NULL;
2359 : }
2360 :
2361 : #ifdef CONFIG_ACPI
2362 : struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2363 :
2364 : void
2365 : pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2366 : bool pci_pr3_present(struct pci_dev *pdev);
2367 : #else
2368 : static inline struct irq_domain *
2369 : pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
2370 : static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; }
2371 : #endif
2372 :
2373 : #ifdef CONFIG_EEH
2374 : static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2375 : {
2376 : return pdev->dev.archdata.edev;
2377 : }
2378 : #endif
2379 :
2380 : void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns);
2381 : bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2382 : int pci_for_each_dma_alias(struct pci_dev *pdev,
2383 : int (*fn)(struct pci_dev *pdev,
2384 : u16 alias, void *data), void *data);
2385 :
2386 : /* Helper functions for operation of device flag */
2387 : static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2388 : {
2389 : pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2390 : }
2391 : static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2392 : {
2393 : pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2394 : }
2395 : static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2396 : {
2397 : return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2398 : }
2399 :
2400 : /**
2401 : * pci_ari_enabled - query ARI forwarding status
2402 : * @bus: the PCI bus
2403 : *
2404 : * Returns true if ARI forwarding is enabled.
2405 : */
2406 : static inline bool pci_ari_enabled(struct pci_bus *bus)
2407 : {
2408 : return bus->self && bus->self->ari_enabled;
2409 : }
2410 :
2411 : /**
2412 : * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2413 : * @pdev: PCI device to check
2414 : *
2415 : * Walk upwards from @pdev and check for each encountered bridge if it's part
2416 : * of a Thunderbolt controller. Reaching the host bridge means @pdev is not
2417 : * Thunderbolt-attached. (But rather soldered to the mainboard usually.)
2418 : */
2419 : static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2420 : {
2421 : struct pci_dev *parent = pdev;
2422 :
2423 : if (pdev->is_thunderbolt)
2424 : return true;
2425 :
2426 : while ((parent = pci_upstream_bridge(parent)))
2427 : if (parent->is_thunderbolt)
2428 : return true;
2429 :
2430 : return false;
2431 : }
2432 :
2433 : #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH)
2434 : void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type);
2435 : #endif
2436 :
2437 : /* Provide the legacy pci_dma_* API */
2438 : #include <linux/pci-dma-compat.h>
2439 :
2440 : #define pci_printk(level, pdev, fmt, arg...) \
2441 : dev_printk(level, &(pdev)->dev, fmt, ##arg)
2442 :
2443 : #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2444 : #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2445 : #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2446 : #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2447 : #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
2448 : #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2449 : #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2450 : #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2451 :
2452 : #define pci_notice_ratelimited(pdev, fmt, arg...) \
2453 : dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg)
2454 :
2455 : #define pci_info_ratelimited(pdev, fmt, arg...) \
2456 : dev_info_ratelimited(&(pdev)->dev, fmt, ##arg)
2457 :
2458 : #define pci_WARN(pdev, condition, fmt, arg...) \
2459 : WARN(condition, "%s %s: " fmt, \
2460 : dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2461 :
2462 : #define pci_WARN_ONCE(pdev, condition, fmt, arg...) \
2463 : WARN_ONCE(condition, "%s %s: " fmt, \
2464 : dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2465 :
2466 : #endif /* LINUX_PCI_H */
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