Line data Source code
1 : // SPDX-License-Identifier: GPL-2.0
2 : /*
3 : * Copyright (C) 2018-2020 Christoph Hellwig.
4 : *
5 : * DMA operations that map physical memory directly without using an IOMMU.
6 : */
7 : #include <linux/memblock.h> /* for max_pfn */
8 : #include <linux/export.h>
9 : #include <linux/mm.h>
10 : #include <linux/dma-map-ops.h>
11 : #include <linux/scatterlist.h>
12 : #include <linux/pfn.h>
13 : #include <linux/vmalloc.h>
14 : #include <linux/set_memory.h>
15 : #include <linux/slab.h>
16 : #include "direct.h"
17 :
18 : /*
19 : * Most architectures use ZONE_DMA for the first 16 Megabytes, but some use
20 : * it for entirely different regions. In that case the arch code needs to
21 : * override the variable below for dma-direct to work properly.
22 : */
23 : unsigned int zone_dma_bits __ro_after_init = 24;
24 :
25 0 : static inline dma_addr_t phys_to_dma_direct(struct device *dev,
26 : phys_addr_t phys)
27 : {
28 0 : if (force_dma_unencrypted(dev))
29 : return phys_to_dma_unencrypted(dev, phys);
30 0 : return phys_to_dma(dev, phys);
31 : }
32 :
33 0 : static inline struct page *dma_direct_to_page(struct device *dev,
34 : dma_addr_t dma_addr)
35 : {
36 0 : return pfn_to_page(PHYS_PFN(dma_to_phys(dev, dma_addr)));
37 : }
38 :
39 0 : u64 dma_direct_get_required_mask(struct device *dev)
40 : {
41 0 : phys_addr_t phys = (phys_addr_t)(max_pfn - 1) << PAGE_SHIFT;
42 0 : u64 max_dma = phys_to_dma_direct(dev, phys);
43 :
44 0 : return (1ULL << (fls64(max_dma) - 1)) * 2 - 1;
45 : }
46 :
47 0 : static gfp_t dma_direct_optimal_gfp_mask(struct device *dev, u64 dma_mask,
48 : u64 *phys_limit)
49 : {
50 0 : u64 dma_limit = min_not_zero(dma_mask, dev->bus_dma_limit);
51 :
52 : /*
53 : * Optimistically try the zone that the physical address mask falls
54 : * into first. If that returns memory that isn't actually addressable
55 : * we will fallback to the next lower zone and try again.
56 : *
57 : * Note that GFP_DMA32 and GFP_DMA are no ops without the corresponding
58 : * zones.
59 : */
60 0 : *phys_limit = dma_to_phys(dev, dma_limit);
61 0 : if (*phys_limit <= DMA_BIT_MASK(zone_dma_bits))
62 : return GFP_DMA;
63 0 : if (*phys_limit <= DMA_BIT_MASK(32))
64 0 : return GFP_DMA32;
65 : return 0;
66 : }
67 :
68 0 : static bool dma_coherent_ok(struct device *dev, phys_addr_t phys, size_t size)
69 : {
70 0 : dma_addr_t dma_addr = phys_to_dma_direct(dev, phys);
71 :
72 0 : if (dma_addr == DMA_MAPPING_ERROR)
73 : return false;
74 0 : return dma_addr + size - 1 <=
75 0 : min_not_zero(dev->coherent_dma_mask, dev->bus_dma_limit);
76 : }
77 :
78 0 : static struct page *__dma_direct_alloc_pages(struct device *dev, size_t size,
79 : gfp_t gfp)
80 : {
81 0 : int node = dev_to_node(dev);
82 0 : struct page *page = NULL;
83 0 : u64 phys_limit;
84 :
85 0 : WARN_ON_ONCE(!PAGE_ALIGNED(size));
86 :
87 0 : gfp |= dma_direct_optimal_gfp_mask(dev, dev->coherent_dma_mask,
88 : &phys_limit);
89 0 : page = dma_alloc_contiguous(dev, size, gfp);
90 0 : if (page && !dma_coherent_ok(dev, page_to_phys(page), size)) {
91 : dma_free_contiguous(dev, page, size);
92 : page = NULL;
93 : }
94 0 : again:
95 0 : if (!page)
96 0 : page = alloc_pages_node(node, gfp, get_order(size));
97 0 : if (page && !dma_coherent_ok(dev, page_to_phys(page), size)) {
98 0 : dma_free_contiguous(dev, page, size);
99 0 : page = NULL;
100 :
101 0 : if (IS_ENABLED(CONFIG_ZONE_DMA32) &&
102 0 : phys_limit < DMA_BIT_MASK(64) &&
103 0 : !(gfp & (GFP_DMA32 | GFP_DMA))) {
104 0 : gfp |= GFP_DMA32;
105 0 : goto again;
106 : }
107 :
108 : if (IS_ENABLED(CONFIG_ZONE_DMA) && !(gfp & GFP_DMA)) {
109 : gfp = (gfp & ~GFP_DMA32) | GFP_DMA;
110 : goto again;
111 : }
112 : }
113 :
114 0 : return page;
115 : }
116 :
117 : static void *dma_direct_alloc_from_pool(struct device *dev, size_t size,
118 : dma_addr_t *dma_handle, gfp_t gfp)
119 : {
120 : struct page *page;
121 : u64 phys_mask;
122 : void *ret;
123 :
124 : gfp |= dma_direct_optimal_gfp_mask(dev, dev->coherent_dma_mask,
125 : &phys_mask);
126 : page = dma_alloc_from_pool(dev, size, &ret, gfp, dma_coherent_ok);
127 : if (!page)
128 : return NULL;
129 : *dma_handle = phys_to_dma_direct(dev, page_to_phys(page));
130 : return ret;
131 : }
132 :
133 0 : void *dma_direct_alloc(struct device *dev, size_t size,
134 : dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
135 : {
136 0 : struct page *page;
137 0 : void *ret;
138 0 : int err;
139 :
140 0 : size = PAGE_ALIGN(size);
141 0 : if (attrs & DMA_ATTR_NO_WARN)
142 0 : gfp |= __GFP_NOWARN;
143 :
144 0 : if ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) &&
145 0 : !force_dma_unencrypted(dev)) {
146 0 : page = __dma_direct_alloc_pages(dev, size, gfp & ~__GFP_ZERO);
147 0 : if (!page)
148 : return NULL;
149 : /* remove any dirty cache lines on the kernel alias */
150 0 : if (!PageHighMem(page))
151 0 : arch_dma_prep_coherent(page, size);
152 0 : *dma_handle = phys_to_dma_direct(dev, page_to_phys(page));
153 : /* return the page pointer as the opaque cookie */
154 0 : return page;
155 : }
156 :
157 0 : if (!IS_ENABLED(CONFIG_ARCH_HAS_DMA_SET_UNCACHED) &&
158 : !IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) &&
159 0 : !dev_is_dma_coherent(dev))
160 : return arch_dma_alloc(dev, size, dma_handle, gfp, attrs);
161 :
162 : /*
163 : * Remapping or decrypting memory may block. If either is required and
164 : * we can't block, allocate the memory from the atomic pools.
165 : */
166 0 : if (IS_ENABLED(CONFIG_DMA_COHERENT_POOL) &&
167 : !gfpflags_allow_blocking(gfp) &&
168 : (force_dma_unencrypted(dev) ||
169 : (IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) && !dev_is_dma_coherent(dev))))
170 : return dma_direct_alloc_from_pool(dev, size, dma_handle, gfp);
171 :
172 : /* we always manually zero the memory once we are done */
173 0 : page = __dma_direct_alloc_pages(dev, size, gfp & ~__GFP_ZERO);
174 0 : if (!page)
175 : return NULL;
176 :
177 0 : if ((IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) &&
178 : !dev_is_dma_coherent(dev)) ||
179 : (IS_ENABLED(CONFIG_DMA_REMAP) && PageHighMem(page))) {
180 : /* remove any dirty cache lines on the kernel alias */
181 : arch_dma_prep_coherent(page, size);
182 :
183 : /* create a coherent mapping */
184 : ret = dma_common_contiguous_remap(page, size,
185 : dma_pgprot(dev, PAGE_KERNEL, attrs),
186 : __builtin_return_address(0));
187 : if (!ret)
188 : goto out_free_pages;
189 : if (force_dma_unencrypted(dev)) {
190 : err = set_memory_decrypted((unsigned long)ret,
191 : 1 << get_order(size));
192 : if (err)
193 : goto out_free_pages;
194 : }
195 : memset(ret, 0, size);
196 : goto done;
197 : }
198 :
199 0 : if (PageHighMem(page)) {
200 : /*
201 : * Depending on the cma= arguments and per-arch setup
202 : * dma_alloc_contiguous could return highmem pages.
203 : * Without remapping there is no way to return them here,
204 : * so log an error and fail.
205 : */
206 : dev_info(dev, "Rejecting highmem page from CMA.\n");
207 : goto out_free_pages;
208 : }
209 :
210 0 : ret = page_address(page);
211 0 : if (force_dma_unencrypted(dev)) {
212 : err = set_memory_decrypted((unsigned long)ret,
213 : 1 << get_order(size));
214 : if (err)
215 : goto out_free_pages;
216 : }
217 :
218 0 : memset(ret, 0, size);
219 :
220 0 : if (IS_ENABLED(CONFIG_ARCH_HAS_DMA_SET_UNCACHED) &&
221 : !dev_is_dma_coherent(dev)) {
222 : arch_dma_prep_coherent(page, size);
223 : ret = arch_dma_set_uncached(ret, size);
224 : if (IS_ERR(ret))
225 : goto out_encrypt_pages;
226 : }
227 0 : done:
228 0 : *dma_handle = phys_to_dma_direct(dev, page_to_phys(page));
229 0 : return ret;
230 :
231 : out_encrypt_pages:
232 : if (force_dma_unencrypted(dev)) {
233 : err = set_memory_encrypted((unsigned long)page_address(page),
234 : 1 << get_order(size));
235 : /* If memory cannot be re-encrypted, it must be leaked */
236 : if (err)
237 : return NULL;
238 : }
239 : out_free_pages:
240 : dma_free_contiguous(dev, page, size);
241 : return NULL;
242 : }
243 :
244 0 : void dma_direct_free(struct device *dev, size_t size,
245 : void *cpu_addr, dma_addr_t dma_addr, unsigned long attrs)
246 : {
247 0 : unsigned int page_order = get_order(size);
248 :
249 0 : if ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) &&
250 0 : !force_dma_unencrypted(dev)) {
251 : /* cpu_addr is a struct page cookie, not a kernel address */
252 0 : dma_free_contiguous(dev, cpu_addr, size);
253 0 : return;
254 : }
255 :
256 0 : if (!IS_ENABLED(CONFIG_ARCH_HAS_DMA_SET_UNCACHED) &&
257 : !IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) &&
258 0 : !dev_is_dma_coherent(dev)) {
259 : arch_dma_free(dev, size, cpu_addr, dma_addr, attrs);
260 : return;
261 : }
262 :
263 : /* If cpu_addr is not from an atomic pool, dma_free_from_pool() fails */
264 0 : if (IS_ENABLED(CONFIG_DMA_COHERENT_POOL) &&
265 : dma_free_from_pool(dev, cpu_addr, PAGE_ALIGN(size)))
266 : return;
267 :
268 0 : if (force_dma_unencrypted(dev))
269 : set_memory_encrypted((unsigned long)cpu_addr, 1 << page_order);
270 :
271 0 : if (IS_ENABLED(CONFIG_DMA_REMAP) && is_vmalloc_addr(cpu_addr))
272 : vunmap(cpu_addr);
273 0 : else if (IS_ENABLED(CONFIG_ARCH_HAS_DMA_CLEAR_UNCACHED))
274 : arch_dma_clear_uncached(cpu_addr, size);
275 :
276 0 : dma_free_contiguous(dev, dma_direct_to_page(dev, dma_addr), size);
277 : }
278 :
279 0 : struct page *dma_direct_alloc_pages(struct device *dev, size_t size,
280 : dma_addr_t *dma_handle, enum dma_data_direction dir, gfp_t gfp)
281 : {
282 0 : struct page *page;
283 0 : void *ret;
284 :
285 0 : if (IS_ENABLED(CONFIG_DMA_COHERENT_POOL) &&
286 : force_dma_unencrypted(dev) && !gfpflags_allow_blocking(gfp))
287 : return dma_direct_alloc_from_pool(dev, size, dma_handle, gfp);
288 :
289 0 : page = __dma_direct_alloc_pages(dev, size, gfp);
290 0 : if (!page)
291 : return NULL;
292 0 : if (PageHighMem(page)) {
293 : /*
294 : * Depending on the cma= arguments and per-arch setup
295 : * dma_alloc_contiguous could return highmem pages.
296 : * Without remapping there is no way to return them here,
297 : * so log an error and fail.
298 : */
299 : dev_info(dev, "Rejecting highmem page from CMA.\n");
300 : goto out_free_pages;
301 : }
302 :
303 0 : ret = page_address(page);
304 0 : if (force_dma_unencrypted(dev)) {
305 : if (set_memory_decrypted((unsigned long)ret,
306 : 1 << get_order(size)))
307 : goto out_free_pages;
308 : }
309 0 : memset(ret, 0, size);
310 0 : *dma_handle = phys_to_dma_direct(dev, page_to_phys(page));
311 0 : return page;
312 : out_free_pages:
313 : dma_free_contiguous(dev, page, size);
314 : return NULL;
315 : }
316 :
317 0 : void dma_direct_free_pages(struct device *dev, size_t size,
318 : struct page *page, dma_addr_t dma_addr,
319 : enum dma_data_direction dir)
320 : {
321 0 : unsigned int page_order = get_order(size);
322 0 : void *vaddr = page_address(page);
323 :
324 : /* If cpu_addr is not from an atomic pool, dma_free_from_pool() fails */
325 0 : if (IS_ENABLED(CONFIG_DMA_COHERENT_POOL) &&
326 : dma_free_from_pool(dev, vaddr, size))
327 : return;
328 :
329 0 : if (force_dma_unencrypted(dev))
330 : set_memory_encrypted((unsigned long)vaddr, 1 << page_order);
331 :
332 0 : dma_free_contiguous(dev, page, size);
333 : }
334 :
335 : #if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \
336 : defined(CONFIG_SWIOTLB)
337 0 : void dma_direct_sync_sg_for_device(struct device *dev,
338 : struct scatterlist *sgl, int nents, enum dma_data_direction dir)
339 : {
340 0 : struct scatterlist *sg;
341 0 : int i;
342 :
343 0 : for_each_sg(sgl, sg, nents, i) {
344 0 : phys_addr_t paddr = dma_to_phys(dev, sg_dma_address(sg));
345 :
346 0 : if (unlikely(is_swiotlb_buffer(paddr)))
347 0 : swiotlb_tbl_sync_single(dev, paddr, sg->length,
348 : dir, SYNC_FOR_DEVICE);
349 :
350 0 : if (!dev_is_dma_coherent(dev))
351 0 : arch_sync_dma_for_device(paddr, sg->length,
352 : dir);
353 : }
354 0 : }
355 : #endif
356 :
357 : #if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \
358 : defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) || \
359 : defined(CONFIG_SWIOTLB)
360 0 : void dma_direct_sync_sg_for_cpu(struct device *dev,
361 : struct scatterlist *sgl, int nents, enum dma_data_direction dir)
362 : {
363 0 : struct scatterlist *sg;
364 0 : int i;
365 :
366 0 : for_each_sg(sgl, sg, nents, i) {
367 0 : phys_addr_t paddr = dma_to_phys(dev, sg_dma_address(sg));
368 :
369 0 : if (!dev_is_dma_coherent(dev))
370 0 : arch_sync_dma_for_cpu(paddr, sg->length, dir);
371 :
372 0 : if (unlikely(is_swiotlb_buffer(paddr)))
373 0 : swiotlb_tbl_sync_single(dev, paddr, sg->length, dir,
374 : SYNC_FOR_CPU);
375 :
376 0 : if (dir == DMA_FROM_DEVICE)
377 0 : arch_dma_mark_clean(paddr, sg->length);
378 : }
379 :
380 0 : if (!dev_is_dma_coherent(dev))
381 : arch_sync_dma_for_cpu_all();
382 0 : }
383 :
384 0 : void dma_direct_unmap_sg(struct device *dev, struct scatterlist *sgl,
385 : int nents, enum dma_data_direction dir, unsigned long attrs)
386 : {
387 0 : struct scatterlist *sg;
388 0 : int i;
389 :
390 0 : for_each_sg(sgl, sg, nents, i)
391 0 : dma_direct_unmap_page(dev, sg->dma_address, sg_dma_len(sg), dir,
392 : attrs);
393 0 : }
394 : #endif
395 :
396 0 : int dma_direct_map_sg(struct device *dev, struct scatterlist *sgl, int nents,
397 : enum dma_data_direction dir, unsigned long attrs)
398 : {
399 0 : int i;
400 0 : struct scatterlist *sg;
401 :
402 0 : for_each_sg(sgl, sg, nents, i) {
403 0 : sg->dma_address = dma_direct_map_page(dev, sg_page(sg),
404 0 : sg->offset, sg->length, dir, attrs);
405 0 : if (sg->dma_address == DMA_MAPPING_ERROR)
406 0 : goto out_unmap;
407 0 : sg_dma_len(sg) = sg->length;
408 : }
409 :
410 : return nents;
411 :
412 0 : out_unmap:
413 0 : dma_direct_unmap_sg(dev, sgl, i, dir, attrs | DMA_ATTR_SKIP_CPU_SYNC);
414 0 : return 0;
415 : }
416 :
417 0 : dma_addr_t dma_direct_map_resource(struct device *dev, phys_addr_t paddr,
418 : size_t size, enum dma_data_direction dir, unsigned long attrs)
419 : {
420 0 : dma_addr_t dma_addr = paddr;
421 :
422 0 : if (unlikely(!dma_capable(dev, dma_addr, size, false))) {
423 0 : dev_err_once(dev,
424 : "DMA addr %pad+%zu overflow (mask %llx, bus limit %llx).\n",
425 : &dma_addr, size, *dev->dma_mask, dev->bus_dma_limit);
426 0 : WARN_ON_ONCE(1);
427 0 : return DMA_MAPPING_ERROR;
428 : }
429 :
430 : return dma_addr;
431 : }
432 :
433 0 : int dma_direct_get_sgtable(struct device *dev, struct sg_table *sgt,
434 : void *cpu_addr, dma_addr_t dma_addr, size_t size,
435 : unsigned long attrs)
436 : {
437 0 : struct page *page = dma_direct_to_page(dev, dma_addr);
438 0 : int ret;
439 :
440 0 : ret = sg_alloc_table(sgt, 1, GFP_KERNEL);
441 0 : if (!ret)
442 0 : sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0);
443 0 : return ret;
444 : }
445 :
446 0 : bool dma_direct_can_mmap(struct device *dev)
447 : {
448 0 : return dev_is_dma_coherent(dev) ||
449 : IS_ENABLED(CONFIG_DMA_NONCOHERENT_MMAP);
450 : }
451 :
452 0 : int dma_direct_mmap(struct device *dev, struct vm_area_struct *vma,
453 : void *cpu_addr, dma_addr_t dma_addr, size_t size,
454 : unsigned long attrs)
455 : {
456 0 : unsigned long user_count = vma_pages(vma);
457 0 : unsigned long count = PAGE_ALIGN(size) >> PAGE_SHIFT;
458 0 : unsigned long pfn = PHYS_PFN(dma_to_phys(dev, dma_addr));
459 0 : int ret = -ENXIO;
460 :
461 0 : vma->vm_page_prot = dma_pgprot(dev, vma->vm_page_prot, attrs);
462 :
463 0 : if (dma_mmap_from_dev_coherent(dev, vma, cpu_addr, size, &ret))
464 : return ret;
465 :
466 0 : if (vma->vm_pgoff >= count || user_count > count - vma->vm_pgoff)
467 : return -ENXIO;
468 0 : return remap_pfn_range(vma, vma->vm_start, pfn + vma->vm_pgoff,
469 : user_count << PAGE_SHIFT, vma->vm_page_prot);
470 : }
471 :
472 4 : int dma_direct_supported(struct device *dev, u64 mask)
473 : {
474 4 : u64 min_mask = (max_pfn - 1) << PAGE_SHIFT;
475 :
476 : /*
477 : * Because 32-bit DMA masks are so common we expect every architecture
478 : * to be able to satisfy them - either by not supporting more physical
479 : * memory, or by providing a ZONE_DMA32. If neither is the case, the
480 : * architecture needs to use an IOMMU instead of the direct mapping.
481 : */
482 4 : if (mask >= DMA_BIT_MASK(32))
483 : return 1;
484 :
485 : /*
486 : * This check needs to be against the actual bit mask value, so use
487 : * phys_to_dma_unencrypted() here so that the SME encryption mask isn't
488 : * part of the check.
489 : */
490 0 : if (IS_ENABLED(CONFIG_ZONE_DMA))
491 : min_mask = min_t(u64, min_mask, DMA_BIT_MASK(zone_dma_bits));
492 0 : return mask >= phys_to_dma_unencrypted(dev, min_mask);
493 : }
494 :
495 0 : size_t dma_direct_max_mapping_size(struct device *dev)
496 : {
497 : /* If SWIOTLB is active, use its maximum mapping size */
498 0 : if (is_swiotlb_active() &&
499 0 : (dma_addressing_limited(dev) || swiotlb_force == SWIOTLB_FORCE))
500 0 : return swiotlb_max_mapping_size(dev);
501 : return SIZE_MAX;
502 : }
503 :
504 0 : bool dma_direct_need_sync(struct device *dev, dma_addr_t dma_addr)
505 : {
506 0 : return !dev_is_dma_coherent(dev) ||
507 0 : is_swiotlb_buffer(dma_to_phys(dev, dma_addr));
508 : }
509 :
510 : /**
511 : * dma_direct_set_offset - Assign scalar offset for a single DMA range.
512 : * @dev: device pointer; needed to "own" the alloced memory.
513 : * @cpu_start: beginning of memory region covered by this offset.
514 : * @dma_start: beginning of DMA/PCI region covered by this offset.
515 : * @size: size of the region.
516 : *
517 : * This is for the simple case of a uniform offset which cannot
518 : * be discovered by "dma-ranges".
519 : *
520 : * It returns -ENOMEM if out of memory, -EINVAL if a map
521 : * already exists, 0 otherwise.
522 : *
523 : * Note: any call to this from a driver is a bug. The mapping needs
524 : * to be described by the device tree or other firmware interfaces.
525 : */
526 0 : int dma_direct_set_offset(struct device *dev, phys_addr_t cpu_start,
527 : dma_addr_t dma_start, u64 size)
528 : {
529 0 : struct bus_dma_region *map;
530 0 : u64 offset = (u64)cpu_start - (u64)dma_start;
531 :
532 0 : if (dev->dma_range_map) {
533 0 : dev_err(dev, "attempt to add DMA range to existing map\n");
534 0 : return -EINVAL;
535 : }
536 :
537 0 : if (!offset)
538 : return 0;
539 :
540 0 : map = kcalloc(2, sizeof(*map), GFP_KERNEL);
541 0 : if (!map)
542 : return -ENOMEM;
543 0 : map[0].cpu_start = cpu_start;
544 0 : map[0].dma_start = dma_start;
545 0 : map[0].offset = offset;
546 0 : map[0].size = size;
547 0 : dev->dma_range_map = map;
548 0 : return 0;
549 : }
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